System to fix post-layout timing and design rules violations

Details System to fix post-layout timing and design rules violations System to fix post-layout timing and design rules violations

1996-12-06

2000-08-08

Lintz, Paul R.

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

716 2, 716 4, 716 18, G06F 1750

Patent

active

06099584&

ABSTRACT:
A programmed design tool and method for determining the placement of components of a very large scale integrated circuit. The present invention is characterized by a common timing engine adapted to check front end high level timing constraints in relation to a netlist representing the circuit.

REFERENCES:
patent: 5425591 (1995-06-01), Ginetti et al.
patent: 5572436 (1996-11-01), Dangelo et al.
patent: 5910897 (1999-06-01), Dangelo
Timing modeling of datapath layout for synthesis. Ginetti, A. Verilog HDL conference, 1994.

Affiliated with

Also associated with

Rating

System to fix post-layout timing and design rules violations does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with System to fix post-layout timing and design rules violations, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System to fix post-layout timing and design rules violations will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1145996