Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2008-05-13
2008-05-13
Trimmings, John P (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S724000, C714S799000, C714S819000, C714S006130, C327S202000, C377S070000
Reexamination Certificate
active
07373572
ABSTRACT:
In one embodiment, an apparatus includes a system pulse latch to generate at least one system latch signal in response to a data input signal and a pulsed system clock signal; a shadow pulse latch to generate at least one shadow latch signal in response to the data input signal and the pulsed system clock signal; and an output joining circuit, coupled to the system pulse latch and the shadow pulse latch, to provide a data output signal in response to the at least one system latch signal and the at least one shadow latch signal.
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Mak Tak M.
Mitra Subhasish
Shipley Paul E.
Zhang Ming
Intel Corporation
Schwabe Williamson & Wyatt P.C.
Trimmings John P
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