Electronic digital logic circuitry – Multifunctional or programmable – Array
Reexamination Certificate
2001-03-23
2003-03-04
Lee, Michael G. (Department: 2876)
Electronic digital logic circuitry
Multifunctional or programmable
Array
C326S038000, C326S039000, C326S041000, C326S083000
Reexamination Certificate
active
06529041
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to the field of integrated circuits, and more specifically to programmable logic devices.
BACKGROUND OF THE INVENTION
Programmable Logic Devices (PLDs) are Integrated Circuits (ICs) that are user configurable and capable of implementing digital logic operations. Logic designers typically use PLDs to implement control logic in electronic systems because they are relatively easy to program, and often can be reprogrammed to update the emulated logic function. This often makes the use of PLDs less costly in comparison to custom hardwired or “application specific” integrated circuits (ASICs).
There are several types of PLDS, including Field Programmable Gate Arrays (FPGAs) and Complex Programmable Logic Devices (CPLDs). FPGAs include configurable logic blocks (CLBs) arranged in rows and columns, IOBs surrounding the CLBs, and programmable interconnect lines that extend between the rows and columns of CLBS. Each CLB includes look-up tables (LUTs) and other configurable circuitry that is programmable to implement a portion of a larger logic function. The CLBs, IOBs and interconnect lines are configured by data stored in a configuration memory of the FPGA. In contrast to the LUT-based CLBs and interconnect lines of FPGAs, CPLDs perform logic using several function blocks that are based on the well-known programmable logic array (PLA) architecture, and utilize a central interconnect matrix to transmit signals between the function blocks. Signals are transmitted into and out of the interconnect switch matrix through input/output blocks (IOBs). However, similar to FPGAs, the input/output function of the IOBs, the logic performed by the function blocks and the signal paths implemented by the interconnect switch matrix are all controlled by configuration data stored in configuration memory of the CPLD.
FIG. 1
is a split-level perspective diagram of a typical CPLD
100
. To simplify the following description, CPLD
100
is functionally separated into a logic plane
110
, which includes the programmable logic resources (circuits) used to implement selected logic operations, and a configuration plane
150
that includes the configuration memory circuits used to store the configuration data utilized to control the programmable logic resources of logic plane
110
. Other simplifications and functional representations are utilized to facilitate the following description.
Referring to the upper portion of
FIG. 1
, for explanatory purposes, logic plane
110
of CPLD
100
includes features common to XC9500 family of CPLDs that are produced by Xilinx, Inc. of San Jose, Calif. In particular, CPLD
100
includes input/output (I/O) terminals
115
, IOBs
120
, an interconnect switch matrix
130
, and several function blocks (FBs)
140
(one shown). IOBs
120
provide buffering for device input and output signals that are applied to I/O terminals
115
. Input signals are passed through IOBs
120
to switch matrix
130
, and selected output signals from FB
140
are fed back into switch matrix
130
. Each FB
140
includes an AND array
142
that logically ANDs input signals received from switch matrix
130
to form product term (P-term) signals that are applied to any of several macrocells
145
. Each macrocell
145
is programmable to generate a sum-of-products term using selected P-term signals. These sum-of-products terms are output from macrocells
145
to IOB
120
(along with optional corresponding output enable signals). Those of ordinary skill in the art generally understand these and other circuits and operations of the programmable circuitry of logic plane
110
(described above).
Referring to the lower portion of
FIG. 1
, configuration plane
150
generally includes a configuration circuit
160
, a non-volatile memory array
170
, and a volatile memory array
180
. Configuration circuit
160
performs several functions associated with configuration plane
150
, including configuration operations during which configuration data is transferred from non-volatile memory array
170
to volatile memory array
180
. Non-volatile (e.g., flash) memory array
170
is provided to persistently store the configuration data that is transferred to volatile memory array
180
during a configuration operation typically performed at device power-up. Volatile memory array
180
includes volatile (e.g., SRAM) configuration memory cells
182
arranged in rows and columns that temporarily store configuration data (e.g., until power to CPLD
100
is terminated). During a configuration operation, configuration circuit
160
routes configuration data from non-volatile memory array
170
to corresponding configuration memory cells
182
of volatile memory array
180
. During subsequent “normal” operation of CPLD
100
, the configuration data stored in volatile memory array
180
is used to control associated programmable logic resources of logic plane
110
via connections
185
(indicated by dashed lines with arrows) in a manner understood by those of ordinary skill in the art, thereby causing CPLD
100
to implement the logic operation defined by the configuration data.
FIG. 2
is a simplified circuit diagram showing portions of CPLD
100
in additional detail. In particular,
FIG. 2
shows a simplified representation of FB
140
, IOB
120
, and configuration memory array (CONF MEM ARRAY)
180
.
Referring to the upper left portion of
FIG. 2
, the illustrated portion of FB
140
includes a portion of logic AND array (&A)
142
, which is depicted as logic AND gates
143
that generate product terms (P-terms) on macrocell input lines
144
, and a portion of a macrocell
145
depicted as including a logic OR gate
147
, a flip-flop (FF)
148
, and an output enable (OE) buffer
149
. Logic OR gate
147
typically receives several P-terms from logic AND array
142
, and generates a sum-of-products (SOP) term that is optionally stored in FF
148
and transmitted to an associated IOB
120
. Similarly, OE buffer
149
receives an associate P-term from logic AND array
142
, and transmits the P-term to IOB
120
.
Referring to the upper right portion of
FIG. 2
, IOB
120
includes an input buffer
121
, an output driver circuit
123
, an output enable (OE) multiplexer
125
, a slew-rate control (SRC) circuit
127
, and a user-programmable ground (UPG) circuit
129
. Input buffer
121
detects and buffers input signals applied to I/O terminal
115
from external devices. Output driver circuit
123
receives the sum-of-products (SOP) term transmitted from macrocell
145
, an output enable (OE) signal from OE multiplexer
125
, and generates an output signal on I/O terminal
115
. OE multiplexer
125
has input terminals respectively connected to receive the P-term transmitted from OE buffer
149
, a global OE control signal, a fixed OE enable (“1”), and a fixed OE disable (“0”). OE multiplexer
125
selectively passes one of these OE signals to the OE terminal of output driver
123
in response to data stored configuration memory array
180
(e.g., in associated configuration data cells
182
-
1
and
182
-
2
). SRC circuit
127
controls the slew rate of the output signals generated by output driver
123
in accordance with configuration data stored in configuration memory array
180
(e.g., in associated configuration data cell
182
-
3
). Finally, when a particular I/O terminal
115
is not utilized in a user's logic operations, UPG circuit
129
allows the user to selectively tie the I/O terminal
115
to ground in accordance with configuration data stored in memory cell
182
-
4
. Other circuitry of IOB
120
and associated connections to configuration memory array
180
are omitted for brevity.
Power control (conservation) is increasingly important in many modern platforms, and particularly in battery powered devices (e.g., laptop computers and personal digital assistants). Power control is typically performed by monitoring the activity in the system, and terminating the power supply provided to idle IC devices of the system.
PLDs, such as PLD
100
(see FIGS.
1
a
Erickson Brian D.
Jenkins, IV Jesse H.
Ng Mark M.
Bever Patrick T.
Casey Michael R.
Lee Michael G.
Paik Steven S.
Xilinx , Inc.
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