System-on-chip with master/slave debug interface

Details System-on-chip with master/slave debug interface System-on-chip with master/slave debug interface

2011-01-11

2011-01-11

Tu, Christine T (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S037000

Reexamination Certificate

active

07870455

ABSTRACT:
A System-on-Chip (SOC) integrated circuit (IC) debugging system includes a plurality of SOC ICs connected to a shared debug bus. One of the plurality of SOC ICs is a master SOC IC having a master/slave debug interface and a user interface. The master/slave debug interface on the master SOC IC is a bidirectional debug interface operable to send and receive debug data between the SOC ICs and an external host system. The host system is connected to the at least one of the plurality of SOC ICs via the user interface.

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