Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis
Reexamination Certificate
2007-11-13
2007-11-13
Perveen, Rehana (Department: 2116)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
C713S501000, C713S503000
Reexamination Certificate
active
10971947
ABSTRACT:
A method of designing a system on a chip (SoC) to operate with varying latencies and frequencies. A layout of the chip is designed with specific placement of devices, including a bus controller, initiator, and target devices. The time for a signal to propagate from a source device to a destination device is determined relative to a default propagation time. A pipeline stage is then inserted into a bus path between said source device and destination device for each additional time the signal takes to propagate. Each device (i.e., initiators, targets, and bus controller) is designed with logic to control a protocol that functions with a variety of response latencies. With the additional logic, the devices do not need to be changed when pipeline stages are inserted in the various paths. Registers are utilized as the pipeline stages that are inserted within the paths.
REFERENCES:
patent: 6127863 (2000-10-01), Elliott
patent: 6601126 (2003-07-01), Zaidi et al.
patent: 6803851 (2004-10-01), Kramer et al.
patent: 6834378 (2004-12-01), Augsburg et al.
patent: 2004/0010652 (2004-01-01), Adams et al.
Augsburg Victor Roberts
Dieffenderfer James Norris
Drerup Bernard Charles
Hofmann Richard Gerard
Sartorius Thomas Andrew
Brown Michael J.
Dillon & Yudell LLP
Perveen Rehana
Rifai D'Ann N.
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