System of multiplexed data lines in a dynamic random access...

Details System of multiplexed data lines in a dynamic random access... System of multiplexed data lines in a dynamic random access...

2006-08-08

2006-08-08

Lam, David (Department: 2827)

Static information storage and retrieval

Read/write circuit

Multiplexing

C365S189011, C365S230040

Reexamination Certificate

active

07088624

ABSTRACT:
A system of multiplexed data lines in a DRAM integrated circuit includes a switching circuit having two switching states. In one switching state, the data lines connect to a first configuration of data paths as would occur in a typical DRAM integrated circuit. A limited number of spare column select lines are available to repair defective column select lines in the first configuration. In another switching state, the data lines connect to a second configuration of the data paths, doubling the number of spare column select lines available to repair a defective column select line.

REFERENCES:
patent: 5844859 (1998-12-01), Iwamoto et al.
patent: 6385100 (2002-05-01), Noda et al.
patent: 6711067 (2004-03-01), Kablanian
patent: 6798702 (2004-09-01), Tsuji

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