Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Reexamination Certificate
2000-10-13
2004-09-28
Zarneke, David A. (Department: 2827)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
Reexamination Certificate
active
06798058
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a semiconductor device, a mounting substrate and method of manufacturing the mounting substrate, a circuit board, and an electronic instrument.
BACKGROUND ART
Semiconductor devices such as T-CSP (Tape-Chip Scale/Size Package) are known, which use a substrate on which an interconnect pattern is formed. Commonly, a semiconductor chip is mounted on the substrate, and with the electrodes of the semiconductor chip electrically connected to the interconnect pattern, solder balls are provided. The characteristics required of the surface of the interconnect pattern for connecting the electrodes of the semiconductor chip and the characteristics required for providing the solder balls are different. Although the surface of the interconnect pattern requires locally varying characteristics, conventionally the whole of the surface of the interconnect pattern has been subjected to a single plating operation.
DISCLOSURE OF THE INVENTION
The present invention solves the above described problem, and has as its objective the provision of a semiconductor device including an interconnect pattern having portions of its surface with different properties, and similarly a mounting substrate and method of manufacture thereof, a circuit board, and an electronic instrument.
(1) A semiconductor device of the present invention comprises:
a substrate in which a plurality of through holes are formed;
an interconnect pattern formed on the substrate and passing over the through holes;
a first plating layer formed on the interconnect pattern surface opposite to the substrate;
a second plating layer formed on the interconnect pattern surface looking toward the substrate in the through holes;
a semiconductor chip mounted on the substrate and electrically connected to the first plating layer;
a resin provided on the first plating layer; and
a conductive material provided on the second plating layer,
wherein the first and second plating layers have different properties.
According to the present invention, since the first and second plating layers are formed on the interconnect pattern, oxidation of the surface of the interconnect pattern can be prevented, and also the electrical contact resistance can be lowered.
The first and second plating layers have different characteristics. A plating layer having appropriate adhesion properties with a resin and a plating layer having appropriate adhesion with a conductive material commonly require different properties. The present invention provides for this by of the first and second plating layers of different properties.
(2) A semiconductor device of the present invention comprises:
a substrate;
a first interconnect pattern formed on one surface of the substrate;
a second interconnect pattern formed on the other surface of the substrate and electrically connected to the first interconnect pattern;
a first plating layer formed on the first interconnect pattern surface opposite to the substrate;
a second plating layer formed on the second interconnect pattern surface opposite to the substrate;
a semiconductor chip mounted on the substrate and electrically connected to the first plating layer;
a resin provided on the first plating layer; and
a conductive material provided on the second plating layer,
wherein the first and second plating layers have different properties.
According to the present invention, since the first and second plating layers are formed on the first and second interconnect patterns, oxidation of the surface of the first and second interconnect patterns can be prevented, and also electrical contact resistance can be lowered. The first and second plating layers have different characteristics. A plating layer having appropriate adhesion properties with a resin and a plating layer having appropriate adhesion with a conductive material commonly require different properties. The present invention provides for this by means of the first and second plating layers of different properties.
(3) A semiconductor device of the present invention comprises:
a substrate;
an interconnect pattern formed on the substrate;
a first plating layer formed on a first portion of the interconnect pattern surface opposite to the substrate;
a second plating layer formed on a second portion of the interconnect pattern surface opposite to the substrate;
a resin provided on the first plating layers;
a conductive material provided on the second plating layer; and
a semiconductor chip mounted on the substrate and electrically connected to the conductive material,
wherein the first and second plating layers have different properties.
According to the present invention, since the first and second plating layers are formed on the interconnect pattern, oxidation of the surface of the interconnect pattern can be prevented, and the electrical contact resistance can be lowered. The first and second plating layers have different characteristics. A plating layer having appropriate adhesion properties with a resin, and a plating layer having appropriate adhesion with a conductive material commonly require different properties. The present invention provides for this by means of the first and second plating layers of different properties.
(4) In this semiconductor device, the first plating layer may be formed to be thinner than the second plating layer.
By making the plating layer thinner, the adhesion properties with the resin are improved, and if the plating layer is made thicker, excellent bonding with the conductive material is obtained.
(5) in this semiconductor device, the first and second plating layers may be formed of different materials.
The first plating layer can be formed of a material improving the adhesion properties with a resin, and the second plating layer can be formed of a material having excellent bonding with the conductive material.
(6) In this semiconductor device, the resin may be an adhesive, and include conductive particles to constitute an anisotropic conductive material; and the semiconductor chip may be mounted by face-down bonding with the anisotropic conductive material interposed.
According to this, an anisotropic conductive material is provided on the first plating layer, and the first plating layer has appropriate adhesion properties with the adhesive of the anisotropic conductive material. By the formation of th first plating layer, in the face-down bonding of the semiconductor chip, the electrical contact resistance is lowered.
(7) A mounting substrate of the present invention comprises:
a substrate in which a plurality of through holes are formed;
an interconnect pattern formed on the substrate and passing ever the through holes;
a first plating layer formed on the interconnect pattern surface opposite to the substrate; and
a second plating layer formed on the interconnect pattern surface looking toward the substrate in the through holes,
wherein the first and second plating layers have different properties.
According to the prevent invention, since the first and second plating layers are formed on the interconnect pattern, oxidation of the surface of the interconnect pattern can be prevented, and also the electrical contact resistance can be lowered. The first and second plating layers have different characteristics. A plating layer having appropriate adhesion properties with a resin, and a plating layer having appropriate adhesion with a conductive material commonly require different properties. The present invention provides for this by means of the first and second plating layers of different properties.
(8) A mounting substrate of the present invention comprises:
a substrate;
a first interconnect pattern formed on one surface of the substrate;
a second interconnect pattern formed on the other surface of the substrate and electrically connected to the first interconnect pattern;
a first plating layer formed on the first interconnect pattern surface opposite to the substrate; and
a second plating layer formed on the second interconnect pattern surface opposite to the substrate,
wherein the first and second pla
Oliff & Berridg,e PLC
Seiko Epson Corporation
Zarneke David A.
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