System for yield enhancement in programmable logic

Details System for yield enhancement in programmable logic System for yield enhancement in programmable logic

2003-08-15

2004-11-30

Le, Don (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Having details of setting or programming of interconnections...

C326S010000

Reexamination Certificate

active

06825688

ABSTRACT:

BACKGROUND
The present invention generally relates to a system for yield enhancement in programmable logic. More specifically, the present invention relates to a system for enhancing yield by using redundant intellectual property logic blocks.
Yield enhancement is an ongoing challenge with any technology and plays a primary role in achieving profitability. The only way to improve yield on standard cell ASIC/ASSP devices is to eliminate the manufacturing defects. Traditional yield enhancement is costly and time consuming. Additionally, no manufacturing process can eliminate all defects and thus there will always be an underlying baseline defect density.
FIG. 1
shows a typical design which is built with a base configuration that includes intellectual property (IP) logic blocks
20
a
,
20
b
,
20
c
,
20
d
;
22
a
,
22
b
,
22
c
,
22
d
provided on a die. As shown, there are two sets of IP logic blocks, i.e. IP logic block One
20
a
,
20
b
,
20
c
,
20
d
and IP logic block Two
22
a
,
22
b
,
22
c
,
22
d
, and there are four instances of each IP logic block
20
a
,
20
b
,
20
c
,
20
d
;
22
a
,
22
b
,
22
c
,
22
d
provided on the die. Predetermined ones of IP logic block One
20
a
,
20
b
are electrically connected between random combinational logic
24
,
26
by respective lines. The random combinational logic
24
provides inputs into the predetermined ones
20
a
,
20
b
of the IP logic block One. The predetermined ones
20
a
,
20
b
of IP logic block One provide outputs to the random combinational logic
26
. In the design shown in
FIG. 1
, only two
20
a
,
20
b
of the four instances of IP logic block One are required. The remaining two
20
c
,
20
d
instances of IP logic block One are unused. Predetermined ones of IP logic block Two
22
b
,
22
c
,
22
d
are electrically connected between the random combinational logic
24
,
26
. The random combinational logic
24
provides inputs into the predetermined ones
22
b
,
22
c
,
22
d
of the IP logic block Two. The predetermined ones
22
b
,
22
c
,
22
d
of IP logic block Two provide outputs to the random combinational logic
26
. In the design shown in
FIG. 1
, three
22
b
,
22
c
,
22
d
of the four instances of IP logic block Two are required. The remaining one
22
a
of IP logic block Two is unused.
In the example shown in
FIG. 1
, when an electrical test is performed on the die, if IP logic block Two
22
c
fails because of a manufacturing defect, the entire die is considered to be a failure and is therefore not used. This results in lower yield. This is despite the availability of a redundant one
22
a
of IP logic block Two which, had redundant IP logic block Two
22
a
been selected and used, the die would have passed the electrical test.
OBJECTS AND SUMMARY
A general object of an embodiment of the present invention is to provide a system for enhancing yield in programmable logic.
Another general object of an embodiment of the present invention is to provide a system which utilizes redundant logic provided to enhance yield.
A further object of an embodiment of the present invention is to provide a system which provides for lower manufacturing costs.
Briefly, and in accordance with at least one of the foregoing objects, an embodiment of the present invention provides a system for yield enhancement in programmable logic. The system includes first random combinational logic, second random combinational logic, a first set of IP logic blocks, a first controller, a second set of IP logic blocks and a second controller. The first set of IP logic blocks are formed from a plurality of like-formed IP logic blocks. The first controller is electrically connected between the first random combinational logic and each of the IP logic blocks in the first set and electrically connected between each of the IP logic blocks in the first set and the second random combinational logic. The first controller is configured to test the IP logic blocks in the first set for functionality or non-functionality, to identify functional ones of the IP logic blocks in the first set and to provide electrical connections between a predetermined number of the functional IP logic blocks in the first set and the first random combinational logic and between the predetermined number of functional IP logic blocks in the first set and the second random combination logic. The second set of IP logic blocks are formed from a plurality of like-formed IP logic blocks which are different than the first set. The second controller is electrically connected between the first random combinational logic and each of the IP logic blocks in the second set and electrically connected between each of the IP logic blocks in the second set and the second random combinational logic. The second controller is configured to test the IP logic blocks in the second set for functionality or non-functionality, to identify functional ones of the IP logic blocks in the second set and to provide electrical connections between a predetermined number of the functional IP logic blocks in the second set and the first random combinational logic and between the predetermined number of functional IP logic blocks in the second set and the second random combination logic. Each of the controllers are preferably BIST/MUX controllers.


REFERENCES:
patent: 5777887 (1998-07-01), Marple et al.
patent: 5790771 (1998-08-01), Culbertson et al.
patent: 6167558 (2000-12-01), Trimberger
patent: 6201404 (2001-03-01), Reddy et al.
patent: 6545501 (2003-04-01), Bailis et al.

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