System for verifying leaf-cell circuit properties

Details System for verifying leaf-cell circuit properties System for verifying leaf-cell circuit properties

2000-06-27

2002-06-11

Smith, Matthew (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

06405351

ABSTRACT:

CROSS-REFERENCES TO RELATED APPLICATIONS
Not Applicable.
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not Applicable.
BACKGROUND OF THE INVENTION
The present embodiments relate to circuit design, and are more particularly directed to computer-aided circuit design connection verification.
Electronic circuits continue to advance in various manners including application, complexity, and size. These advancements and other factors have led to a circuit design approach that often involves many persons, particularly for designs using large scale integrated circuit (LSI) or very large scale integrated circuit (VLSI) technologies. Often, different persons may have different responsibilities in developing a final integrated circuit. In one approach, a team may be formed where a master designer sets forth various rules to govern some or all types of circuits to be used in an overall design, and then other persons as circuit designers develop smaller circuit designs (or “sub-circuits”) while complying with the master designer's rules. By way of an example a processor device may be designed by such a team and using domino logic, where the master designer establishes various rules to be followed by all domino logic used in any sub-circuit that will form a part of the processor device. To further implement this approach, once each circuit designer has completed his or her designs, then those designs are reviewed to ensure compliance with the master designer's rules. As a result, the master designer's rules often reduce functionality and/or performance problems that otherwise may arise if widespread discretion is given to each individual circuit designer.
While the above approach to circuit design provides the benefits arising from a master control, it also provides certain drawbacks. For example, the techniques for ensuring that the circuit designers have complied with the master designer's rules may be time consuming, tedious, and subject to error. Particularly, often the ultimate responsibility for checking that the circuit designer's designs have complied with the master designer's rules is given solely to the master designer and, thus, can require a deal of effort, time, and attention by the master designer. Further, the master designer in making the compliance evaluation is still subject to human error and, thus, may unintentionally oversee one or more compliance failures. Thus, these failures may remain in the overall circuit design, and may well cause difficulties later in the circuit development, such as once the circuit is reduced to silicon and tested or implemented.
In view of the above, there arises a need to address the drawbacks of circuit design, as is achieved by the preferred embodiments described below.
BRIEF SUMMARY OF THE INVENTION
In the preferred embodiment, there is a computer system. The computer system comprises processing circuitry and storage circuitry for storing a plurality of files. The plurality of files include a circuit description file comprising data describing devices and signals in a circuit. The plurality of files also include a plurality of list expressions relating to one of devices, signals, or devices and signals described by the data in the circuit description. Still further, the plurality of files also include a plurality of rules. The processing circuitry is programmed to perform various steps. These steps include processing the plurality of list expressions to extract a plurality of lists in response to the circuit description. Each of the plurality of lists comprises a non-negative integer number of elements. The programmed steps further include processing the plurality of rules to evaluate one or more of the plurality of lists to verify connection accuracy within the circuit in response to the non-negative integer number of elements. Other circuits, systems, and methods are also disclosed and claimed.


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“CadMOS Design Technology Announces ArctIC™, An Elctrical Rule Checker for SOC Designs,”, 2 pages; Jun. 26, 2000.

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