Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses
Reexamination Certificate
1998-06-25
2001-10-23
Butler, Dennis M. (Department: 2182)
Electrical computers and digital processing systems: support
Synchronization of clock or timing signals, data, or pulses
C713S503000, C709S241000
Reexamination Certificate
active
06308280
ABSTRACT:
BACKGROUND OF THE INVENTION
(a) Field of the Invention
The present invention relates generally to a method of synchronizing discrete electronic components to a common clock source. The discrete electronic components could be two or more circuit boards in a personal computer (PC), and the common clock source could be at a remote transmission station that sends packetized data to the PC. The present invention is useful in achieving synchronization, in calibration with the clock signals transmitted in the data's bitstream, of all separately clocked circuit boards needed to receive and decode the data. The packetized data can include broadcast entertainment-type data, such as the digital video, audio, and information data signals transmitted via a variety of different digital direct broadcast satellite (DBS) systems.
(b) Description of Related Art
Conventional digital broadcast systems include a receiver station that receives and processes transmitted packets of data. One type of receiver station is part of a “wireless digital television” system known commercially by the tradename DSS®. The DSS system, which is utilized by the DIRECTV® broadcast service, allows consumers to receive directly in their homes over 175 television channels broadcast from several powerful satellites. The receiver station includes a small 18-inch satellite dish connected by a cable to an integrated receiver/decoder unit (IRD). The satellite dish is aimed toward the satellites, and the IRD is connected to the user's television in a similar fashion to a conventional cable-TV decoder.
During transmission of a digital broadcast, video, audio, and related information data signals are digitally encoded into a packetized data bitstream using a number of algorithms. The encoded data bitstream is modulated to Ku-band frequency, transmitted to the satellite, and relayed from the satellite to the 18-inch local satellite dish. The satellite dish shifts the Ku-band signal down to an L-band signal which is transmitted through the cable to the IRD.
In the IRD, front-end circuitry receives the L-band signal and converts it to the original digital data stream of video, audio, and related information signals. The incoming digital data bitstream is fed to a transport circuit which performs functions such as channel demultiplexing, decryption, and access determination. A micro-controller controls the overall operation of the IRD, including the selection of parameters, the set-up and control of components, channel selection, viewer access to different programming packages, blocking certain channels, and other functions. The data stream from the transport circuit is sent to the decompression video/audio decoder circuits. The compression and decompression of digital packetized video and audio signals may be accomplished according to the Moving Picture Expert Group (MPEG) standard for performing digital video/audio compression. Thus, the IRD unit typically includes, along with the transport circuit, an MPEG-1 or MPEG-2 video/audio decoder in order to decompress the received compressed video/audio. The decoded data from the MPEG video/audio decoder circuit is sent to a video digital-to-analog NTSC encoder and output drivers to display the broadcast signal on the users television.
An extension of the present DSS IRD system is a PC-based system that allows users to receive and display, directly into their PC's, the same digital video, audio, and related information signals received in the current DSS IRD system. The receiver station in this system includes a local satellite receiver dish similar to that of the current DSS IRD system, but the integrated receiver/decoder (IRD) functions are done within the PC architecture through the use of separate PC circuit boards. The decompressed outputs from these boards are displayed on the PC's monitor.
In general, digital video and audio signals can be transported, processed, and displayed with a high degree of quality and accuracy. The quality of digital broadcasts requires that receiver stations be able to receive and decode signals with a high degree of precision. Therefore, in order to correctly represent digital broadcast data, receiver stations must be accurately synchronized with the incoming broadcast signal's bitstream.
A typical DSS data packet's bitstream can contain, along with the actual broadcast audio/video signal, certain data packets that will be referred to herein for convenience as “time stamp data packets.” Time stamp data packets contain a time stamp which may be defined as a snapshot of the system clock at the transmission facility. In the DSS system, the system clock is at 27 MHZ, and each time stamp is derived from a counter also running at 27 MHZ. The time stamps represent the instantaneous time at which the encoder as measured by the value of a 27 MHZ counter sampled at the time of its transmission. The difference between two successive time stamps represents the number of clock cycles that have occurred at the encoder between the transmission of said time stamps. As such, these time stamps are the crucial means by which the source broadcaster or uplink satellite provider can transmit the timing information of the original signal's source to the local receiver. Synchronization of the broadcast data clock with the receiver/decoder clock(s) allows the receiver station to correctly decode and display the incoming signal through proper buffering of the data. This synchronization requires that the local clocks at the receiver station be collectively locked in frequency with the uplink encoder's internal clock. A lack of timing synchronization between clocks at the receiver station, whether in the transport, audio/video decoder, or display driver, will result in eventual loss of transmitted data through either underflow or overflow of data buffers.
Buffer underflows and overflows do not occur in present DSS IRD's because the IRD typically has only one clock which is coupled to all necessary subsystems. The IRD synchronizes to this clock using known means, and uses this clock to run all necessary circuits within the IRD. The IRD's clock is synchronized by the IRD transport circuit frequency-calibrating or locking to the clock transmitted in the incoming bitstream. The transport locks to the system clock by comparing the difference between successive local transport counter times (latched at the receipt of successive system time stamps) to the difference between the successive received time stamp values. The comparison algorithm allows the local transport clock to lock onto the incoming bitstream's transmitted clock based on this comparison.
The IRD's clock, after calibration within the transport, is then coupled via hardwired connections directly to the audio/video decoder circuit within the IRD. The decoder circuit buffers the data received from the transport. It decodes the data therein buffered and sends the signal to the video encoder which converts the digital data to an analog format for display. Because this hardwired means of direct physical coupling between circuits exists, there is no lack of synchronization between the front-end transport circuit and the downstream circuit such as the MPEG video/audio decoder or the NTSC video encoder. However, in PC-based DSS or DVB systems, a number of size and architectural constraints make direct coupling of clocks to downstream circuits an impractical option. For example, the backplane of a conventional PC is not conducive to sending data in real time with fixed delay. This variable delay in moving data through a PC can be a significant problem.
There is a necessity within a PC's architecture to have the various functions of the current DSS system's integrated receiver/decoder divided among different PC circuit boards. In particular, currently available PC-based DSS receiver stations utilize a separate transport circuit board, which includes the front-end demodulation, FEC, and tuner circuitry of the current IRD, as well as the standard channel demultipl
Casavant Scott
Joseph Kuriacose
Butler Dennis M.
Hughes Electronics Corporation
Sales Michael W.
Whelan John T.
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