System for improving processing efficiency in a pipeline by dela

Details System for improving processing efficiency in a pipeline by dela System for improving processing efficiency in a pipeline by dela

1997-11-26

1999-11-02

An, Meng-Al T.

Electrical computers and digital processing systems: support

Synchronization of clock or timing signals, data, or pulses

713401, 713500, 712220, G06F 1300

Patent

active

059789255

ABSTRACT:
In a pipelined processor, when a conditional branch is effected in accordance with a state of calculation generated by immediately previous instruction, it is necessary for a conventional technique to insert a NOP (no operation) instruction before a conditional branch instruction. This lowers the processing efficiency. In order to solve this problem, a delay circuit generates a clock signal .phi.' which is supplied to a program counter and an instruction memory. The clock signal .phi.' is delayed behind a system clock .phi.. This obviates the need to insert such a NOP instruction and the processing efficiency is improved.

REFERENCES:
patent: 5086500 (1992-02-01), Greub
patent: 5185869 (1993-02-01), Suzuki
patent: 5815017 (1998-09-01), McFarland

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