Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-05-01
2003-11-11
Tsai, Jey (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S381000
Reexamination Certificate
active
06645804
ABSTRACT:
FIELD OF THE INVENTION
The invention is generally related to the field of fabricating integrated circuit capacitors and, more specifically, to improving the efficiency of capacitor fabrication by forming the insulator layer of a capacitor from an anti-reflective coating.
BACKGROUND OF THE INVENTION
Since the invention of integrated circuits, the number of devices on a chip has grown at a near-exponential rate. The fabrication methods of the semiconductor industry have been modified and improved continuously for almost four decades. With each improved method, the capacity of a single semiconductor chip has increased from several thousand devices to hundreds of million devices. Future improvements will require integrated circuit devices such as transistors, capacitors, and connections between devices to become even smaller and more densely populated on the chip.
The increased packing density of the integrated circuit generates numerous challenges to the semiconductor manufacturing process. Every device must be smaller without damaging the operating characteristics of the integrated circuit devices. The requirements of high packing density, low heat generation, and low power consumption, with good reliability and long operation life, must be maintained without any functional degradation. Increased packing density of integrated circuits is usually accompanied by smaller feature size.
As integrated circuits become denser, the techniques for fabricating the semiconductor devices must become more precise. Lithography, for example, is one fabrication technique that may be used to remove particular areas of deposited material to define various components of the semiconductor device. Overall device size, however, has become so small that reflected light could remove a detrimental amount of material from adjacent structures. An anti-reflective coating (ARC) layer may be deposited to reduce or eliminate the possibility of reflected light damaging adjacent structures and to improve the resolution of the lithography process.
In addition to more precise manufacturing techniques, semiconductor fabrication must become more efficient to reduce costs for the consumer and remain competitive with other manufacturers. Each step of the fabrication process consumes time, which increases costs and reduces production volume. Because profits are directly related to production volume, any production delay reduces the profits of a manufacturer.
There are a number of conventional capacitor fabrication processes. Several examples of conventional capacitor fabrication processes are depicted in
FIGS. 1A-1D
. In particular,
FIG. 1A
depicts a typical metal-insulator-metal (MIM) capacitor fabrication process in which a capacitor
10
has a first electrode
12
. A second electrode
14
is separated from the first electrode
12
by a dielectric
16
. The first electrode
12
may have multiple layers
18
and
20
, which may be configured according to the desired performance characteristics of the capacitor
10
. Layer
18
, for example, may be a silicided polysilicon or some other type of semiconductor material. Layer
20
, for example, may be a metal such as tungsten or titanium nitride. This particular configuration of layers
18
,
20
,
22
, may be combined to fabricate a high capacitance capacitor in an integrated circuit.
FIG. 1B
depicts another conventional method of fabricating a capacitor
10
in which the capacitor stack (
12
,
14
,
16
, collectively) is deposited immediately after the first half of the via etch. After the capacitor stack (
12
,
14
,
16
) is deposited and etched, the second half of the via
24
is formed directly above the first half of the via
24
. Fabrication of this particular capacitor
10
, however, requires two additional masking steps. One additional masking step is required for the capacitor stack (
12
,
14
,
16
) and another additional masking step is required to form the upper half of the vias
24
that connect the second electrode
14
to the semiconductor region
18
. The patterning and etching of the capacitor stack (
12
,
14
,
16
) may cause damage to the dielectric
16
, which could cause leakage within the capacitor
10
. Leakage may reduce the performance of the capacitor
10
or cause complete failure of the capacitor
10
.
The conventional capacitor fabrication method depicted in
FIG. 1C
requires only one additional mask. In this particular design, the capacitor stack (
12
,
14
,
16
) is deposited and etched immediately prior to the deposition of the metal layer
26
. A metal top
26
is added over the second electrode
14
. The vias
24
may be formed over the metal top
26
and semiconductor layer
18
may then be deposited. As with the method depicted in
FIG. 1B
, possible damage to the dielectric may occur during the etching of the capacitor stack (
12
,
14
,
16
). Additionally, the topography of the capacitor
10
produced by this method may cause a residue of conducting layer
26
to remain and result in a bypass of electrical current from the second electrode
14
to the first electrode
12
, which renders the capacitor
10
ineffective.
Finally, in the conventional capacitor fabrication process depicted in
FIG. 1D
, the capacitor stack (
12
,
14
,
16
) is deposited and etched immediately after the pattering of the metal layer
18
. The metal patterning step, however, requires deposition of an ARC (Anti-Reflective Coating) to improve resolution of a lithographic patterning process. Therefore, the ARC used on the metal layer
18
must be removed prior to the deposition of the capacitor stack (
12
,
14
,
16
) to allow electrical contact with the first electrode
12
.
SUMMARY OF THE INVENTION
Therefore, a system for forming integrated circuit capacitors that does not add excessive costs or procedures to the fabrication process, is now needed, providing for fabrication of more reliable integrated circuit capacitors while overcoming the aforementioned limitations of conventional methods.
The present invention provides a system for fabricating an integrated circuit capacitor. An electrode layer is formed in the integrated circuit. An anti-reflective coating is deposited over the electrode layer. An electrode top plate is formed over the anti-reflective coating.
REFERENCES:
patent: 6326301 (2001-12-01), Venkatesan et al.
patent: 6429474 (2002-08-01), Gambino et al.
Columbo Luigi
Johnson F. Scott
Prinslow Doug
Taylor Kelly
Tsai Van-Joy
Brady III Wade James
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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