Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output data buffering
Reexamination Certificate
1999-06-10
2002-09-24
Gaffin, Jeffrey (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output data buffering
C710S100000, C714S047300
Reexamination Certificate
active
06457077
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to information processing systems and more particularly to an improved information transfer methodology in a computer related environment.
BACKGROUND OF THE INVENTION
As computer systems and networked computer systems proliferate, and become integrated into more and more information processing systems which are vital to businesses and industries, there is an increasing need for faster information processing and increased data handling capacity. Even with the relatively rapid state-of-the-art advances in processor technology, and the resulting increased processor speeds, a need still exists for faster processors and increased system speeds and bandwidths. As new applications for computers are implemented, new programs are developed and those programs are enriched with new capabilities almost on a daily basis. While such rapid development is highly desirable, there is a capability cost in terms of system speed and bandwidth.
As used herein, the term “bandwidth” is used generally to refer to the amount of information that can be transferred in a given period of time. In transferring information between devices in a computer system, information is frequently temporarily stored in “holding” buffers along the path of the information transfer. Such buffers include bridge buffers which are generally located in bridge circuits connecting devices or busses between which the information is to be transferred. In one example, peripheral component interconnect or “PCI” system bridge circuit buffers are assigned to PCI devices, which are installed in PCI “slots” and coupled to an associated PCI bus. Complex computer systems may include many bridge circuits connected between individual PCI busses or connecting a PCI bus to a system bus. In a PCI system, any of the computer system enhancement devices or adapters are generally included on one or more circuit boards which are mounted or inserted is into PCI “slots”, i.e. into board connector terminals mounted on a system motherboard.
In the past, the “holding” or “in transit” buffers were usually available for any device to utilize, and in some cases, depending on the arbiter, some devices could be temporarily deprived of available buffers because each time a device is granted the bus, the device could find that the “return” buffers are full, in which case the requested transaction is halted until such a time as an appropriate number of transfer buffers are emptied and become available for use in temporarily storing data for another transaction. In systems which include extended bridge circuit architectures, transaction requests which originate from devices on lower order bridges must wait for available buffers at the lower level bridge circuits before such requests can even be moved along the system bridge architecture to the next bridge buffers on the path to system memory or to other PCI or other devices in the system. This process has an inherent latency while waiting for available bridge holding buffers to be freed-up from earlier transactions. Even after a buffer is indicated as being available for use in a new transaction, there can be latency or delay involved in notifying the waiting transactions that the buffers are free and available to be used in passing the transaction request up to the next “higher” bridge on the system data path due to the other current bus activity.
Thus there is a need for an improved methodology and implementing system which enables a more advantageous use of buffer availability in transferring information between devices connected within an information processing system.
SUMMARY OF THE INVENTION
A method and implementing system is provided in which system bridge circuits are enabled to execute, or over-commit, transaction requests from system devices for information transfers which exceed the bridge circuit's current capacity to receive the requested information on its return from a designated target device such as system memory or another system device. The transaction request is moved along the data path to the designated target device and the requested information is returned, in an exemplary embodiment, to the requesting device. The over-commitment is controlled so that, in a well-tuned system, buffer space frees up just in time to accept the read completion data as that data is being returned to the requesting device. In an illustrated embodiment, the amount of over-commitment is programmable and the amount of over-commitment to transaction requests may be automatically adjusted to optimize the information transfer in accordance with the particular system demands and current data transfer traffic levels. The data transfer methodology is illustrated in a PCI system but may be used in many bus protocols and is applicable to information transfers to and from system memory as well as between peer devices.
REFERENCES:
patent: 5867482 (1999-02-01), Kobayashi
patent: 5867686 (1999-02-01), Conner et al.
patent: 5898848 (1999-04-01), Gulick
patent: 5974571 (1999-10-01), Riesenman et al.
patent: 6202101 (2001-03-01), Chin et al.
Kelley Richard A.
Neal Danny Marvin
Thurber Steven Mark
Yanes Adalberto Guillermo
Elamin Abdelmoniem
Gaffin Jeffrey
McBurney Mark E.
Wilder Robert V.
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