Electrical computers and digital processing systems: processing – Processing control – Specialized instruction processing in support of testing,...
Reexamination Certificate
1998-08-14
2001-01-30
An, Meng-Ai T. (Department: 2783)
Electrical computers and digital processing systems: processing
Processing control
Specialized instruction processing in support of testing,...
C714S025000, C714S035000
Reexamination Certificate
active
06182208
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to the field of software debugging programs, and specifically to a new technique to increase the number of break points that can be implemented in read only memories (ROM).
BACKGROUND OF INVENTION
In order to develop software, it is important to have debugging tools to find bugs or errors in the software. One of the important features of a debugger is the ability to set break points on an instruction and get control of the computer program to examine its state when the flow of control of the program reaches the break point. Typical computer systems or peripheral debug diagnostic systems, for example, logic analyzers, implement break points by using individual registers. A register is a memory element storing a plurality of bits. Each bit in the register can be a logical 0 or a logical 1, as is common in digital computer systems. Thus, the break point is defined by a bit pattern of logical 0's and logical 1's called a break point code, which is stored in the register. In general, a debugger is expected to support multiple break points since there might be multiple points of interest to the user. To implement break points, the user first specifies an address (A) to the debugger where the program must break in order to activate the break point. The debugger then replaces the software instruction at address (A) with a break instruction.
Subsequently, during the execution of the computer program, if the break instruction is executed, control is transferred to the debugger which either prints a message or waits for user input. This transfer of control allows a computer operator to then scrutinize various contents of the computer system to examine if the computer system is in a proper state at the time of recognition, that is, at the break point. When the program execution needs to be continued, the break point instruction is replaced with the actual instruction which had originally been present in the computer program. This approach works well when the program to be debugged exists in a memory location which can be written to by the user. However, in embedded systems, the computer program usually resides in read-only memory (ROM), which cannot be written to by the user. Thus, the above approach of replacing the instruction at the break point with a break point instruction is not possible.
One prior art approach of debugging programs in ROM is to always single step the program, as known in the art, and compare the address of the instruction to be executed with a previously-specified list of break points set by the user. Using this approach, any number of break points can be supported in the debugging program without the need for any extra hardware support. However, this single-step approach is rarely used because it is extremely slow. The execution time of the program in a debugging mode is several orders of magnitude slower than the actual program which makes for a very unpleasant debugging experience.
A second alternate prior art approach to debug computer programs that are present in ROM is to provide additional hardware to support break points in ROM. This approach has been used by embedded processors like the ARM, Lucent 1600, Lucent 16000, TI C54X, etc. embedded processors.
Reference is now made to
FIG. 1
which depicts an example of the second prior art approach to debug computer programs that are present in ROM by providing additional hardware to support break points in ROM. In the prior art, a hardware debugging support module
5
consists of a break point address list
7
and a comparator
6
as shown in FIG.
1
. The output of break point address list
7
is connected to comparator
6
within hardware debugging support module
5
. Comparator
6
taps into address bus
14
which transfers information between processor
12
and memory
10
of the computer system. A predetermined user defined list of break point addresses is stored in break point address list
7
. When hardware debugging support module
5
is in operation, comparator
6
compares the actual condition existing on address bus
14
, i.e., the address being passed between processor
12
and memory
10
, with the list of addresses that are stored in break point address list
7
. When comparator
6
finds a match between a signal on address bus
14
and an address stored in break point address list
7
, comparator
6
signals that a break point has been recognized, and hardware debugging support module
5
interrupts processor
12
and transfers control to the debugger. Since the comparison performed by comparator
6
must be done at the speed of processor
12
and the silicon resources needed for storing the list of break point addresses in break point address list
7
is large, prior art processors limit break points to an extremely small and finite number. Generally, only one breakpoint address can be loaded into one of the registers at any one time. Thus, to implement a plurality of break points requires a plurality of break point registers which increases the complexity and cost of the hardware. Generally, break point address list
7
is implemented using one or two registers, thereby limiting the debugger to the use of only one or two break points. Thus, it is desirable to provide for a new technique that allows for the placement of a greater number of break points in ROM with a finite amount of hardware resources.
SUMMARY OF THE INVENTION
The present invention is directed at overcoming the shortcomings of the prior art. Generally speaking, in accordance with the present invention, a system for debugging a computer program, present in read-only memory (ROM) comprises a debugger, a processor, read-only memory, a hardware debugging support module and a bus.
The debugger has a list of “n” user specified break points which it uses to divide a computer program that needs to be debugged into “n+1” regions. Each of these regions has a start address and an end address. The read-only memory is connected to the processor by the bus.
The hardware debugging support module comprises a first register called the range start register, a second register called the range end register and a comparator. The first register contains the start address of a selected region from the “n+1” regions, whereas the second register contains the end address of the selected region. Thus, the first register and the second register define a range of address locations for the computer program. The comparator is connected to the bus, the first register and the second register and monitors addresses traveling on the bus. The hardware debugging support module interrupts the processor and transfers control to the debugger if a specific address on the bus does not fall within the range defined by the first register and the second register. When a specific address on the bus does not fall within the range, the debugger performs a search on the remaining “n+1” regions to see if that specific address lies in any one of those regions. If such a region is found, then the start address and end address of this second region are programmed into the first register and the second register of the hardware debugging support module. However, if the specific address is not found to lie within any of the remaining “n+1” regions, then the debugger transfers control of the computer program to the user because the computer program has reached a break point. The user can now scrutinize the computer program at the break point.
To continue debugging the computer program, after the computer program hits a break point, the comparator is disabled and the computer program is single stepped to execute the instruction at which the break point had been placed. The debugger then performs a search on the remaining “n+1” regions by using the output address obtained as a result of the single-stepping process to determine the region which contains this output address. The start address and end address of this third region are then programmed into the first register and the second register of
Fajardo Lincoln
Jinturkar Sanjay
Peri Ramesh V.
Wilshire Jay
An Meng-Ai T.
El-Hady Nabil
Lucent Technologies - Inc.
Stroock & Stroock & Lavan LLP
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