System for controlling transistor spacer width

Details System for controlling transistor spacer width System for controlling transistor spacer width

2000-06-23

2002-06-25

Lund, Jeffrie R. (Department: 1763)

Adhesive bonding and miscellaneous chemical manufacture

Differential fluid etching apparatus

With measuring, sensing, detection or process control means

C118S663000, C118S695000, C118S696000, C118S698000, C118S699000, C118S719000

Reexamination Certificate

active

06409879

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to the field of semiconductor processing, and, more particularly, to a method for reducing junction capacitance using a halo implant photomask.
2. Description of the Related Art
Semiconductor devices, such as transistors, are formed through a series of steps. First a gate is formed over a portion of a substrate. Various implants are then conducted to form source/drain (S/D) regions of the transistor. In an N type transistor, N type dopants are implanted in a P type substrate. In a P type transistor, an N type well is typically formed in a portion of the substrate, and the gate is formed over a portion of the N type well. P type dopants are then implanted to form the S/D regions.
Typically, several implantation steps are used to form the transistor. In the following discussion, fabrication of an N type transistor is described. First, a lightly doped drain (LDD) implant is performed using an N type dopant, such as arsenic. Next, a halo implant is performed using a P type dopant, such as boron. The halo implant is used to reduce short channel effects associated with the transistor. Short channel effects cause the threshold voltage of the transistor to decrease as the geometry shrinks. Typically, at least a portion of the halo implant is performed at an angle so that some of the dopant is implanted beneath the gate. Following the halo implant, spacers are formed on the gate, and a S/D implant is performed with an N type dopant, such as phosphorous.
The spacers are typically formed by depositing a conformal insulative layer over the gate and surrounding substrate and anisotropically etching the conformal insulative layer. Because the spacer etch is anisotropic, the portions of the insulative layer on the sides of the gate are not removed, thus leaving the spacer. The endpoint for stopping the spacer etch is typically determined by monitoring (e.g., by optical emission spectroscopy) the makeup of the plasma used to perform the etch. When the substrate is exposed during the etch, the makeup of the plasma changes. This change is detected and the etch is stopped. Due to variations in the initial thickness of the insulative layer, the conformality of the insulative layer, and the accuracy of the endpointing process, the final width of the spacers formed is not always constant.
The effective channel length L
eff
of the resulting gate depends a great deal on the width of the spacers, because the source/drain implant is performed after their formation. The effective channel length is an influential factor in determining the maximum speed of the transistors, and thus, the overall speed rating of the device (e.g., microprocessor). Lack of effective spacer width control widens the speed distributions of the devices produced. Faster devices have a higher market value; hence, wider speed variations equate to reduced revenue.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
SUMMARY OF THE INVENTION
One aspect of the present invention is seen in a method for controlling spacer width in a semiconductor device. A substrate having a gate formed thereon is provided. An insulative layer is formed over at least a portion of the substrate. The insulative layer covers the gate. The thickness of the insulative layer is measured. A portion of the insulative layer to be removed is determined based on the measured thickness of the insulative layer. The portion of the insulative layer is removed to define a spacer on the gate.
Another aspect of the present invention is seen in a processing line for forming a spacer on a gate disposed on a substrate. The processing line includes a deposition tool, a thickness metrology tool, and automatic process controller, and a spacer etch tool. The deposition tool is adapted to form an insulative layer over at least a portion of the substrate. The insulative layer covers the gate. The thickness metrology tool is adapted to measure the thickness of the insulative layer. The automatic process controller is adapted to determine a portion of the insulative layer to be removed based on the measured thickness of the insulative layer. The spacer etch tool is adapted to remove the portion of the insulative layer to define a spacer on the gate.


REFERENCES:
patent: 4789426 (1988-12-01), Pipkin
patent: 5291415 (1994-03-01), Zarowin et al.
patent: 5387311 (1995-02-01), Hall et al.
patent: 5474647 (1995-12-01), Poultney et al.
patent: 5510281 (1996-04-01), Ghezzo et al.
patent: 5656533 (1997-08-01), Kim
patent: 5814563 (1998-09-01), Ding et al.
patent: 5833817 (1998-11-01), Tsai et al.
patent: 5856224 (1999-01-01), Sheu
patent: 5863824 (1999-01-01), Gardner et al.
patent: 6133132 (2000-10-01), Toprac et al.
patent: 02003243 (1990-01-01), None
patent: 07176729 (1995-07-01), None

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