Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses
Reexamination Certificate
2000-09-29
2004-07-13
Lee, Thomas (Department: 2116)
Electrical computers and digital processing systems: support
Synchronization of clock or timing signals, data, or pulses
C713S401000, C713S500000, C713S600000, C714S709000
Reexamination Certificate
active
06763475
ABSTRACT:
FIELD OF INVENTION
The present invention generally relates to glitching (i.e., intermediate logic transitions in a logic circuit resulting from changes in logical states), and more specifically to a system for controlling the effects of glitching using level sensitive latches.
BACKGROUND OF THE INVENTION
Large buses are common internal structures in integrated circuit designs. These buses are needed to carry groups of common signals for data and control. For example, an instruction bus delivers the instruction to be executed to the instruction decoder inside a processor ASIC. During normal operation, these multiplexed or tri-state bus structures are prone to decode “glitching,” which results from rapid intermediate logic state transitions from ‘1’ to ‘0’ or vice versa, before settling to a final logic state. These migratory or transient logic states occur due to combinatorial decoding and are unavoidable due to transport delays and differential timing of the logic inputs.
Functionally, with synchronous designs, glitches are harmless since intermediate states occur just after the active clock edge and settle out to a stable value before the end of the clock cycle. However, the wasted power consumption caused by these fruitless transitions are a concern in power sensitive applications. The problem becomes magnified on large buses since the capacitive load is great and the fanout cone can be large, thereby propagating the glitching transitional data all over the chip. With faster and faster speed designs now approaching nano-meter dimensions, it is also desirable to reduce the noise caused by buses to prevent adverse electrical effects such as crosstalk.
Many prior art approaches exist for solving problems of this nature. Most involve manipulating the combinatorial decodes to prevent the transmission of glitching transitional data. For example, decodes can be gated to an “off-state,” wherein contents settle. This gating is carefully constructed to avoid the transmission of glitching transitional data. However, this approach can be difficult to implement due to the wide variance of timing that occurs when a design is placed, routed and fabricated into a device. Moreover, such designs may add to the critical path timing of certain paths.
Registering of bus signals before driving the bus load is also a common technique, but is not always possible in all designs due to the extra functional clock cycle delay imposed by the logic change. Gating of register clocks is another approach which can reduce flip flop transitions and hence the chance of glitching. However, the gating of register clocks causes testing issues and timing problems which effect a wide variety of registers.
In tri-state bus implementations, the glitching problem has been addressed by manipulating the tri-state enable logic. In this regard, when a tri-state buffer is enabled (i.e., turned on to drive), the enable signal is carefully controlled to turn on only after the data input to the buffer has settled. However, tri-state logic creates numerous problem with testing and bus contention especially in ASIC designs. Consequently, multiplexed buses are typically chosen.
The present invention provides an easy to implement and effective means for minimizing or eliminating the transmission of “transitioning” data resulting from changes in the logic state of combinatorial logic, and for improving hold times.
SUMMARY OF THE INVENTION
According to the present invention there is provided a method for controlling the effects of glitching transitions on internal buses, using a latch to prevent the propagation of the glitching transitions.
According to another aspect of the present invention there is provided a system for controlling data flow between a first digital circuit and a second digital circuit, comprising: at least one latch for receiving and storing data from the first digital circuit, and outputting the stored data to the second digital circuit; and at least one latch enable circuit for controlling the opening and closing of the at least one latch, wherein said at least one latch receives and stores data from the first digital circuit when open, and retains the stored data when closed, wherein said latch enable circuit closes the at least one latch in response to a transition of a first clock signal and opens the at least one latch in response to a transition of a second clock signal, wherein the second clock signal is delayed relative to the first clock signal.
According to another aspect of the present invention there is provided a system for controlling data flow between a first digital circuit and a second digital circuit, comprising: at least one means for latching data received from the first digital circuit, and outputting the latched data to the second digital circuit; and at least one means for latch enablement for controlling the opening and closing of the at least one means for latching data, wherein said at least one means for latching data receives data from the first digital circuit when open, and retains the latched data when closed, wherein said means for latch enablement closes the at least one means for latching data in response to a transition of a first clock signal and opens the at least one means for latching data in response to a transition of a second clock signal, wherein the second clock signal is delayed relative to the first clock signal.
According to another aspect of the present invention there is provided a method for controlling transfer of data between a first digital circuit and a second digital circuit via a latch arranged therebetween to transfer data stored in the latch from the first digital circuit to the second digital circuit, wherein opening and closing of the latch is controlled by a latch enable circuit, the method comprising the steps of: closing the latch in response to a transition of a first clock signal; and opening the latch to receive and store data from the first digital circuit in response to a transition of a second clock signal, wherein the second clock signal is delayed relative to the first clock signal.
An advantage of the present invention is the provision of system for controlling the effects of glitching transitions to reduce power reduction.
Another advantage of the present invention is the provision of a system for controlling the effects of glitching transitions, which extends a hold time, thereby preventing race conditions on a bus.
Another advantage of the present invention is the provision of system for controlling the effects of glitching transitions which has low hardware costs for implementation.
Still another advantage of the present invention is the provision of a system for controlling the effects of glitching transitions that it is easily scalable to accommodate large buses.
Still another advantage of the present invention is the provision of a system for controlling the effects of glitching transitions that is applicable to a variety of different digital circuit arrangements.
Yet another advantage of the present invention is the provision of a system for controlling the effects of glitching transitions that is simple to implement and easy to use.
Still other advantages of the invention will become apparent to those skilled in the art upon a reading and understanding of the following detailed description, accompanying drawings and appended claims.
REFERENCES:
patent: 4797575 (1989-01-01), Lofgren
patent: 5113098 (1992-05-01), Teymouri
patent: 5185537 (1993-02-01), Creedon et al.
patent: 5231636 (1993-07-01), Rasmussen
patent: 5315181 (1994-05-01), Schowe
patent: 5387825 (1995-02-01), Cantrell et al.
patent: 5774005 (1998-06-01), Partovi et al.
patent: 5949258 (1999-09-01), Jeong
patent: 6016066 (2000-01-01), Ilkbahar
patent: 6055587 (2000-04-01), Asami et al.
patent: 6075392 (2000-06-01), Sandner
patent: 01226212 (1989-09-01), None
Cappello, P.; LaPaugh, A.; Steiglitz, K.; “Optimal choice of intermediate latching to maximize throughput in VLSI circuits”, Acoustics, Speech, and Signal Processing [also IEEE Trans. on Sig. Proc], IEEE T
Cisco Technology Inc.
Lee Thomas
Trujillo James K.
Tucker Ellis & West LLP
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