Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
1995-11-21
2003-08-05
Thai, Tuan V. (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S154000, C711S212000
Reexamination Certificate
active
06604173
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to cache memories, and more particularly to controlling access to external cache memories in a computer system.
BACKGROUND OF THE INVENTION
One of the typical components to increase the speed of computer systems are cache memories. The cache memories serve as smaller, faster storage areas and include data that is also stored in the main memory in a computer system, and usually contain data that may be more frequently accessed by the computer system to increase the speed at which the computer's processor operates. Various methods and systems have been conventionally used to organize the correspondence between the main memory and cache memory structures. One form of organizing a cache memory is known as direct-mapping.
In direct-mapping, the data held in the main memory is designated as a series of blocks. For example, in a 64 Kbyte main memory addressable by a 16-bit address line, 4 Kbyte blocks with 16 words per block is suitable. Similarly, a cache memory is divided into a series of blocks, for example, a 2 Kbyte cache memory is suitably divided into 128 blocks with 16 words per block. Because of the reduced size of the cache memory in comparison to the main memory, multiple blocks within the main memory are allotted the same potential blocks for storage within the cache memory. For example, with the 64 Kbyte main memory and 2 Kbyte cache memory described, blocks
0
,
128
,
256
, etc. of the main memory are suitably mapped into block
0
of the cache memory. With this configuration, the address of the data in main memory is used as an indexer for the cache memory. With the example described above, the 16-bit address line is suitably divided to have seven bits address the 128 blocks of the cache memory, four lowest order bits to identify which of the 16 bytes within each cache memory block is desired, and the remaining five most significant bits as a tag field. Thus, the unique identifier provided by the tag field is utilized to determine whether a tag field of a block in the cache memory matches an incoming tag field of an address.
With direct-mapping schemes, the bit-by-bit comparison performed between the tag field of the address and the stored tags of the cache memory data verifies the presence of the data in the cache memory. While direct-mapping schemes are adequate for many systems, in some systems, cache memories of varying sizes may be used. In such systems, the number of bits required to address the cache memory data varies, so that the size of the tag field varies for each different cache memory size. Special considerations, such as the use of a mode bit, are often used to designate which size tag field is suitable for the cache memory being accessed. Unfortunately, the complexity of such systems is increased thus reducing the speed of access to the cache memories.
A need exists for a flexible and efficient system for accessing cache memories that accommodates cache memories of differing size. The present invention addresses such a need.
SUMMARY OF THE INVENTION
The present invention provides method and system aspects to control access to external cache memories of differing size. In a method aspect for controlling access to at least one external cache memory in a processing system, at least one external cache memory having a number of lines of data and a number of bytes per line of data, the method includes determining a smallest cache memory size for use in at least one external cache memory, and configuring a tag array of at least one external cache memory to support the smallest determined cache memory size.
The method further includes having the tag array include a plurality of tag fields, each tag field associated with each line of data of at least one external cache memory, and utilizing the tag array to determine whether data being accessed resides in at least one external cache memory. In addition, utilizing the tag array further includes determining whether a match exists between a tag of an incoming address and the tag array. Also, configuring each tag field further includes allotting a number of bits for each tag field, such that the number of bits is the number of bits required to uniquely identify the data in the smallest determined cache memory size.
In a system aspect of the present invention, a system for controlling access to at least one external cache memory in a processing system, at least one external cache memory having a number of lines of data and a number of bytes per line of data, includes a circuit for configuring each tag field of a plurality of tag fields in a tag array in at least one external cache memory to have a number of bits sufficient to support a smallest determined cache memory, and utilizing each tag field to determine whether data being accessed resides in at least one external cache memory.
With the present invention, a flexible and efficient system for accessing cache memories that accommodates cache memories of differing size is achieved. The system capably handles cache memories of any size above a predetermined smallest size by effectively recognizing and taking to advantage the relationship between the size of the cache memory structure and width of the tag field. As the cache memory size decreases, the tag field width, i.e., the number of bits used to store the tag field data, increases, and vice versa. Thus, the present invention configures each tag field of the tag array to hold a maximum number of bits for a smallest cache memory size, such that the ability to access larger-sized cache memories is not diminished.
REFERENCES:
patent: 5014195 (1991-05-01), Farrell et al.
patent: 5175833 (1992-12-01), Yarkoni et al.
patent: 5542062 (1996-07-01), Taylor et al.
patent: 5553258 (1996-09-01), Godiwala et al.
Cheong Hoichi
Hicks Dwain A.
Lattimore George M.
Liu Pei-chun P.
International Business Machines - Corporation
Thai Tuan V.
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