Hoichi Cheong

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Apparatus and method for fast unified interrupt recovery and bra

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Commitment control or register bypass
Patent

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Apparatus and method for reducing the number of rename registers

Electrical computers and digital processing systems: processing – Processing architecture – Superscalar
Patent

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Apparatus and method for selecting entries from an array

Static information storage and retrieval – Magnetic bubbles – Guide structure
Patent

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Cache lock mechanism with speculative allocation

Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate

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Cache lock mechanism with speculative allocation

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate

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Profile ID: LFUS-PAI-P-522972

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