Static information storage and retrieval – Read/write circuit – Precharge
Reexamination Certificate
2002-04-29
2004-11-09
Le, Thong Q. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Precharge
Reexamination Certificate
active
06816423
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor memory devices, and more particularly, to a system for controlling pre-charge levels in a memory device to reduce the effect of leakage currents.
BACKGROUND OF THE INVENTION
Semiconductor devices, such as memory devices, are commonly used as information storage devices in digital systems. As the amount of information that needs to be stored increases, it has become increasingly important to have an efficient way of accessing such memory devices.
Generally, memory read or write operations are initiated in response to external signals provided to the memory by a controller, such as a processor. In most cases, the amount of information that needs to be transferred during a memory access is large. In addition, the rate at which the information is propagated from a processor to a memory device and vice versa continues to increase. Therefore, increasing performance demands are being placed on the ability to read and write information to memory devices.
In Flash memory technology, there exist double bit core cells that can store two data bits, which result in very high density memory products.
FIG. 1
shows a diagram
100
of a typical double bit core cell. The core cell
100
has two data bits (A, B) that can be programmed, erased, or read. If it is desired to read bit A, then terminal NA is operated as a “source” and terminal NB is operated as a “drain.” To read bit B, the functions of terminals NA and NB are reversed.
FIG. 2
shows a portion of a memory device
200
that includes three double bit cells (
202
,
204
,
206
). If it is desired to read bit A, then terminal L
2
operates as a drain. Assuming bits C and D are erased, then terminal L
3
must be charged-up in order to prevent leakage current between terminals L
2
and L
3
. If there is leakage current, it will influence the reading of bit A.
One technique that has been used to charge-up terminal L
3
is to use the same type of sense amplifier for L
2
and L
3
. When the same sense amplifiers are used for L
2
and L
3
, then the voltage at L
2
and L
3
should be the same. However, in practical applications this is not the case. For example, the voltage on L
2
depends on the status of bit A. If bit A is erased, then the voltage at L
2
is lower than the voltage at L
3
due to bit A current. Furthermore, the voltage at L
3
is also influenced by bit E and bit F even if L
4
is floating. Even the voltage difference between L
2
and L
3
is very small, there is some leakage current, which will affect the reading of bit A. Therefore, using one more sense amplifiers does not solve the leakage problem.
Therefore, it would be desirable to have a way to operate a dual bit memory without incurring the problems caused by leakage currents as outlined above.
SUMMARY OF THE INVENTION
The present invention includes a system to operate cells in a memory device without incurring problems associated with leakage currents. As a result of the operation of one or more embodiments included in the present invention, it is possible to control pre-charge levels of memory cells to avoid leakage current problems.
In one embodiment of the present invention, an apparatus is provided for controlling a pre-charge level of a dual bit memory cell in a memory device. The apparatus comprises a first terminal coupled between first and second memory cells, and a second terminal coupled to the second memory cell. The apparatus also comprises a mirror circuit coupled to the first and second terminals, wherein the mirror circuit operates to maintain the same voltage level on the first and second terminals.
In another embodiment included in the present invention, a method is provided for controlling a pre-charge level of a dual bit memory cell in a memory device. The memory device includes a first terminal coupled between first and second memory cells and a second terminal coupled to the second memory cell. The method comprises steps of inputting a level at the first terminal to an input of a mirror circuit, mirroring the level at the input of the mirror circuit at an output of the mirror circuit, and inputting the level at the output of the mirror circuit to the second terminal.
REFERENCES:
patent: 5056063 (1991-10-01), Santin et al.
patent: 5359571 (1994-10-01), Yu
patent: 5535167 (1996-07-01), Hazani
patent: 6480419 (2002-11-01), Lee
Fujitsu Limited
Le Thong Q.
Sheppard Mullin Richter & Hampton LLP
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