System for communications where first priority data transfer...

Details System for communications where first priority data transfer... System for communications where first priority data transfer...

2000-10-03

2003-06-03

Gaffin, Jeffrey (Department: 2182)

Electrical computers and digital data processing systems: input/

Input/output data processing

Concurrent input/output processing and data transfer

C710S021000, C710S029000, C710S032000, C710S036000, C710S040000, C710S117000, C370S232000, C370S235000, C709S235000

Reissue Patent

active

RE038134

ABSTRACT:

FIELD OF THE INVENTION
The present invention pertains to a novel system for prioritized communication within a computer system. More particularly, the present invention relates to a method and system for a prioritized communication function which allows communications between multiple devices of a computer system to be organized such that higher priority communications receive a preferential allocation of resources within the computer system.
BACKGROUND OF THE INVENTION
In the past, computers were primarily applied to processing rather mundane, repetitive numerical and/or textual tasks involving number-crunching, spread sheeting, and word processing. These simple tasks merely entailed entering data from a keyboard, processing the data according to some computer program, and then displaying the resulting text or numbers on a computer monitor and perhaps later storing these results in a magnetic disk drive. However, today's computer systems are much more advanced, versatile, and sophisticated. Especially since the advent of digital media applications and the Internet, computers are now commonly called upon to accept and process data from a wide variety of different formats ranging from audio to video and even realistic computer-generated three-dimensional graphic images. A partial list of applications involving these digital media applications include the generation of special effects for movies, computer animation, real-time simulations, video teleconferencing, Internet-related applications, computer games, telecommuting, virtual reality, high-speed databases, real-time interactive simulations, medical diagnostic imaging, and the like.
The proliferation of digital media applications is due to the fact that information can be more readily conveyed and comprehended with pictures and sounds rather than with text or numbers. Video, audio, and three-dimensional graphics render a computer system more user friendly, dynamic, and realistic. However, the added degree of complexity for the design of new generations of computer systems necessary for processing these digital media applications is tremendous. The ability of handling digitized audio, video, and graphics requires that vast amounts of data be processed at extremely fast speeds. An incredible amount of data must be processed every second in order to produce smooth, fluid, and realistic full-motion displays on a computer screen. Additional speed and processing power is needed in order to provide the computer system with high-fidelity stereo sound and real-time, and interactive capabilities. Otherwise, if the computer system is too slow to handle the requisite amount of data, its rendered images would tend to be small, grainy and otherwise blurry. Furthermore, movement in these images would likely be jerky and disjointed because its update rate is too slow. Sometimes, entire video frames might be dropped. Hence, speed is of the essence in designing modern, state-of-the-art computer systems.
One of the major bottlenecks in designing fast, high-performance computer systems is the method in which the various hardware devices comprising the computer system communicate with each other. This method is dictated by the “bus” architecture of the computer system. A “bus” is comprised of a set of wires that is used to electrically interconnect the various semiconductor chips and hardware devices of the computer system. The bus acts as a shared conduit over which electronic signals are conducted, enabling the various components to communicate with each other.
FIG. 1
shows a typical prior art bus architecture
100
. Virtually all of today's computer systems use this same type of busing scheme. Computer system
100
includes a central processing unit (CPU)
101
coupled to a host bridge/memory controller
102
, which in turn coupled to a random access memory system (hereafter memory)
103
and a bus
104
. Various devices
105
-
108
are coupled to computer system
100
via bus
104
.
Bus
104
is used to electronically interconnect the CPU
101
with the memory
103
via bridge/memory controller
102
. CPU
101
also accesses the various other devices
105
-
108
via bus
104
. Bus
104
is comprised of a set of physical wires which are used to convey digital data, address information for specifying the destination of the data, control signals, and timing/clock signals. For instance, CPU
101
may generate a request to retrieve certain data stored on hard disk
105
. This read request is communicated via bridge/memory controller
102
and via bus
104
to hard disk
105
. Upon receipt of this read request, hard disk
105
accesses and reads the desired data from its internal media and subsequently sends the data back over bus
104
to the CPU
101
. Once the CPU is finished processing the data, it can be sent via bus
104
for output by a device coupled to bus
104
(e.g., graphics output device
106
or network adapter device
107
).
One constraint with this prior art bus architecture is the fact that it is a “shared” arrangement. All of the components
105
-
108
share the same bus
104
. They each rely on bus
104
to meet their individual communication needs. However, bus
104
can transfer only a finite amount of data to any one of devices
105
-
108
in any given time period (e.g., typically measured as millions of bytes per second, or MB/sec). The total amount of data which can be transferred in a given time period is often referred to as the data transfer “bandwidth” or simply bandwidth. The total amount of data which can be transferred over bus
104
in a given time period is referred to as the bandwidth of bus
104
, and for a typical computer system is often between 100 to 300 MBytes/sec.
Computer system
100
uses a relatively simple arbitration scheme to allocate bus bandwidth. Hence, if bus
101
is currently busy transmitting signals between two of the devices (e.g., device
105
and device
106
), then all the other devices (e.g., memory
102
, device
104
, and CPU
103
) must wait their turn until that transaction is complete and bus
104
again becomes available. If a conflict arises, an arbitration circuit, usually residing in bridge/memory controller
102
, resolves which of the devices
105
-
108
gets priority of access to bus
104
. Because of this, it becomes very difficult to predict and account for how the bandwidth is allocated among devices using the bus. There is not an efficient means for controlling bus bandwidth allocation among competing devices. In computer system
100
, as in other typical computer systems, it is difficult to efficiently coordinate among competing devices for use of the computer system's bus.
In addition to coordinating for use of the computer system's bus, another constraint results from the fact that individual hardware devices have internal schemes for coordinating among competing data requests. For example, hard disk
105
may be accessing frames of video data for output to graphics device
106
for display. Subsequently, hard disk
105
receives a request to store data output from CD-ROM
108
and a request for data from network adapter device
107
. Since, data retrieval and output by hard disk
105
cannot occur instantaneously, the competing requests are placed into an internal queue. The competing data requests are subsequently serviced by hard disk
105
serially. Thus, when graphics device
106
requests the next frames of data, the request must wait in the internal queue with the other requests. Because of this, a video stream played by graphics device
106
could drop several frames, or even fail entirely. Even though access to the video data may be a much higher priority to the user than the data request from CD-ROM
108
or network adapter
107
, the higher priority request must wait in the internal queue with all other lower priority requests.
These constraints make it difficult for current computer systems (e.g., computer systems in accordance with computer system
100
) to run the latest, most real-time critical, software applications. As such, applic

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