Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses
Reexamination Certificate
2000-01-03
2003-06-17
Lee, Thomas (Department: 2185)
Electrical computers and digital processing systems: support
Synchronization of clock or timing signals, data, or pulses
C710S052000, C710S057000, C710S061000, C710S310000, C713S503000, C713S600000
Reexamination Certificate
active
06581164
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates, generally, to systems and processes for tracking the timing of asynchronous systems in a manner that accommodates timing irregularities in a reference system while maintaining a stable output in a tracking system, and in particular embodiments, to methods for tracking the read timing of a video encoder to the write timing of a video decoder, and systems incorporating the same.
2. Description of Related Art
It is often desirable to transfer data between two or more systems that are not synchronized to a common timing source. For example, in video signal processing systems, video data from a video source such as a video cassette recorder (VCR:) may be transferred to a video display device for viewing. Because the VCR and the video display device do not have a common timing source, the timing between these two asynchronous systems must be carefully controlled, or tracked, to minimize data transfer errors. For purposes of illustration, the timing of a video signal processing system will be discussed in detail below, but it should be understood that the basic timing issues inherent in a video signal processing system are equally applicable to other asynchronous systems.
Modern video signal processing systems often combine audio, video, and graphics for viewing on a video display device. In such multi-media systems, graphics information must be integrated into the audio and video information present within an analog video signal. Integrating graphics information into a video signal is often more easily accomplished in the digital domain. Thus, it is desirable to decode the analog video signal into digital form, integrate the graphics information, and encode the combined signal back into an analog form compatible with typical video display devices.
There are several different standardized formats for the analog video signal. One such format is NTSC (National Television System Committee), which is used in the United States and Japan. Another is PAL (Phase Alternation Lines), which is used in Great Britain and Europe. A third is SECAM, which is used in France, Russia and other parts of Europe. For purposes of simplifying the following description, only NTSC timing will be discussed. However, the other formats are similar and have only slight variations, and therefore the following discussion is conceptually applicable to all formats.
As shown in
FIG. 1
, within an analog video signal is a single “line”
10
of analog video information. A line
10
is typically comprised of a front porch
12
, a horizontal synchronization pulse (H
sync
)
14
, a subcarrier burst
16
, and serial pixel data
18
.
Subcarrier burst
16
is a sample of the reference subcarrier used to modulate U and V color signals and generate chrominance signals within serial pixel data
18
. The U color signal is modulated with one phase of the reference subcarrier, while the V color signal is modulated with a 90° phase-shifted version of the reference subcarrier. The U and V color signals are added together to form the chrominance portion of the video signal. When decoding the analog video signal, the reference subcarrier is re-created by phase-locking a frequency source (at the subcarrier burst rate) to subcarrier burst
16
. The re-created reference subcarrier is then used to demodulate the chrominance signals within serial pixel data
18
and recover the U and V color signals. In the NTSC standard, the reference subcarrier is defined to have a frequency of 3.579545 MHz±10 Hz, with 227.5 reference subcarrier cycles per line. The line frequency in NTSC is therefore equal to approximately 3.579545 MHz÷227.5 cycles per line, or approximately 15.734 kHz.
Pixel data
18
contains information representing one horizontal line of pixels on a video display device. Serial pixel data
18
is followed by a second H
sync
14
, signifying the end of the present line and the start of a new line. Thus, H
syncs
14
mark the boundary between successive lines
10
of analog video information. The voltage swing of the typical analog video signal is approximately 1.3 volts maximum.
One “field” of video information is defined as a sequence of lines representing one refresh of a video display device from top to bottom. A vertical synchronization pulse (V
sync
) marks the boundary between successive fields of video information. For NTSC, there are 262.5 lines from one V
sync
to the next. Thus, the field frequency is approximately 15.734 kHz÷262.5, or approximately 59.94 Hz. As illustrated in
FIG. 2
, V
sync
20
is not a single pulse, but rather is a signal superimposed on the analog video signal comprised of a series of equalization pulses
22
, each pulse being approximately one-half of a line long, followed by a series of wider serration pulses
24
, followed by another series of equalization pulses
22
. The actual vertical synchronization event
26
occurs at the boundary between the first set of equalization pulses
22
and the sequence of serration pulses
24
. V
sync
20
represents the start of a vertical blanking region (V
blanking
)
28
, the time during which the electron beam in tube-type video display devices resets from the bottom to the top of the display device. V
blanking
28
includes V
sync
20
and
11
more lines of H
sync
, that follow V
sync
(see reference character
30
;
FIG. 2
not drawn to scale). At the end of V
blanking
28
, an H
sync
14
marks the beginning of the first active line in the new field.
Other timing signals derived from the analog video signal are generated within a typical video signal processing system, including a horizontal active signal (H
active
) and a vertical active signal (V
active
). Referring to
FIG. 1
, when H
active
32
is asserted (high in the example of FIG.
1
), serial pixel data
18
is being communicated in an active region
34
of a line
10
of analog video information. Associated with H
active
32
is horizontal blanking region (H
blanking
)
38
, which occurs when serial pixel data
18
is not being communicated in the active region of a line
10
(i.e., when H
active
32
is not asserted). Referring to
FIG. 2
, when V
active
36
is asserted (high in the example of
FIG. 2
) a field of video information is being refreshed, and the video signal is not in V
blanking
region
28
.
Video information is often interlaced, which means that during the refreshing of a field, only every other line on a video display device is refreshed. Two fields of video data are therefore needed to completely refresh the screen of a video display device. For example,
FIG. 3
illustrates one method of interlacing using the NTSC format and a conventional picture tube embodiment of a video display device which focuses a beam to excite phosphors R, G and B and produce a color for each pixel. In
FIG. 3
, after a first V
blalnking
followed by an H
sync
14
is received, H
active
32
is asserted and line
1
is refreshed. Line
1
concludes with H
sync
14
followed by H
blanking
38
, during which time the beam moves to the beginning of line
3
. H
active
32
is again asserted, and line
3
is then refreshed. This process continues for lines
5
,
7
,
9
, etc. (the “odd” field). After 262.5 lines of the odd field are refreshed, a V
sync
20
will be received with the first serration pulse occurring in the middle of a line rather than at the beginning of the line (the last half line of the odd field), signifying the end of the odd field. A V
blanking
period
28
is then entered, during which time the beam returns to the top of the video display device. When an H
sync
14
signifying the start of the next active line is received, lines
0
,
2
,
4
,
6
, etc. (the “even” field) are refreshed. When all 262.5 lines of the even field have been written, the bottom of the video display device is again reached, and a V
sync
is received in alignment with an H
sync
, which causes the beam to move back to the top of the display device and reset to line
1
. The complete refreshing of a full
Felts, III Benjamin Edwin
Scott Havard Lee
Shakeel Asif
Conexant Systems Inc.
Connolly Mark
Lee Thomas
Procopio Cory Hargreaves & Savitch LLP
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