System controlling interface timing in memory module and...

Details System controlling interface timing in memory module and... System controlling interface timing in memory module and...

2005-10-24

2008-09-02

Bataille, Pierre-Michel (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

C711S154000, C710S006000, C710S305000, C713S400000, C713S500000

Reexamination Certificate

active

07421558

ABSTRACT:
A memory system for controlling interface timing in a memory module and a related timing control method are disclosed. The memory system comprises a memory module having a memory module controller configured to control interface timing of a plurality of memory devices in accordance with memory information and memory signal information. The memory information includes memory initialization information and interface timing information for the plurality of memory devices.

REFERENCES:
patent: 6535411 (2003-03-01), Jolin et al.
patent: 2001/0003198 (2001-06-01), Wu
patent: 2002/0144173 (2002-10-01), Jeddeloh
patent: 2003/0105932 (2003-06-01), David et al.
patent: 2003/0156473 (2003-08-01), Sinclair et al.
patent: 2003/0231537 (2003-12-01), Stark
patent: 2005/0190193 (2005-09-01), Freker et al.

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