Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2011-01-18
2011-01-18
Tsai, Sheng-Jen (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711SE12023
Reexamination Certificate
active
07873789
ABSTRACT:
In a system controller including a CPU-issued request queue having a circuit that processes plural requests having identical addresses not to be inputted to the CPU-issued request queue, a latest request other than a cache replace request is retained by an input-request retaining section. Consequently, even if an address of an issued request for cache replace request matches an address of a request retained by the CPU-issued request queue, the issued request for the cache replace request is not retried but is queued in the CPU-issued request queue when the address of the issued request for the cache replace request does not match the entire address retained by the input-request retaining section.
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Hataida Makoto
Hosokawa Yuka
Ishizuka Takaharu
Itou Daisuke
Owaki Takeshi
Fujitsu Limited
Staas & Halsey , LLP
Tsai Sheng-Jen
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