System architectures for and methods of scheduling on-chip...

Details System architectures for and methods of scheduling on-chip... System architectures for and methods of scheduling on-chip...

2007-01-09

2009-06-09

Barnie, Rexford (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Signal level or switching threshold stabilization

C327S538000

Reexamination Certificate

active

07545165

ABSTRACT:
Integrated circuit (IC) system architectures that allow for the reduction of on-chip or across-chip transient noise budgets by providing a means to avoid simultaneous high current demand events from at least two functional logic blocks, i.e., noise contributors, are disclosed. Embodiments of the IC systems architectures include at least one noise event arbiter and at least two noise contributor blocks. A method of scheduling on-clip noise events to avoid simultaneous active transient noise events may include, but is not limited to: the noise event arbiter receiving simultaneously multiple requests-to-operate from multiple noise contributers; the noise event arbiter determining when each noise contributer may execute operations based on a pre-established dI/dt budget; and the noise event arbiter notifying each noise contributer as to when permission is granted to execute its operations.

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patent: 6675246 (2004-01-01), Molnar et al.
patent: 2003/0221055 (2003-11-01), Okada
patent: 2004/0034749 (2004-02-01), Jeddeloh
patent: 2004/0046611 (2004-03-01), Uneme
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