System and method to asynchronously test RAMs

Details System and method to asynchronously test RAMs System and method to asynchronously test RAMs

2007-03-27

2007-03-27

Lamarre, Guy (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C714S030000

Reexamination Certificate

active

09940299

ABSTRACT:
A system and method for testing the random access memory of a computer system is disclosed. A memory-testing engine is embedded in the utility bus controller of an application specific integrated circuit, which is coupled to a random access memory in need of testing. Upon receiving an initiation signal over a bus from the central processing unit, the memory-testing engine begins writing data to a targeted area of the memory, and then reading back the stored data and comparing the data to what was sent. Having the memory-testing engine distributed to the memory's being tested allows several memory devices to be tested simultaneously.

REFERENCES:
patent: 6370661 (2002-04-01), Miner
patent: 6501690 (2002-12-01), Satoh
patent: 2002/0078408 (2002-06-01), Chambers et al.

Affiliated with

Also associated with

Rating

System and method to asynchronously test RAMs does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with System and method to asynchronously test RAMs, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System and method to asynchronously test RAMs will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3799955