Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1995-08-24
1997-09-02
Swann, Tod R.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711122, G06F 1208
Patent
active
056641478
ABSTRACT:
Within a data processing system implementing L1 and L2 caches and stream filters and buffers, prefetching of cache lines is performed in a progressive manner. In one mode, data may not be prefetched. In a second mode, two cache lines are prefetched wherein one line is prefetched into the L1 cache and the next line is prefetched into a stream buffer. In a third mode, more than two cache lines are prefetched at a time. As a result, additional cache lines are progressively prefetched to a data cache as the sequentiality of the accessing of cache lines in memory is demonstrated through sequential addressing requests along a data stream. Furthermore, the stream is physically distributed. In other words, at least one line, but not all lines, of the stream are placed within the cache.
REFERENCES:
patent: 4980823 (1990-12-01), Liu
patent: 5146578 (1992-09-01), Zangenehpour
patent: 5317718 (1994-05-01), Jouppi
patent: 5345560 (1994-09-01), Miura et al.
patent: 5353419 (1994-10-01), Touch et al.
patent: 5364391 (1994-11-01), Westberg
patent: 5371870 (1994-12-01), Goodwin et al.
patent: 5381539 (1995-01-01), Yanai et al.
patent: 5388247 (1995-02-01), Goodwin et al.
patent: 5473764 (1995-12-01), Chi
patent: 5490113 (1996-02-01), Tatosian et al.
patent: 5537568 (1996-07-01), Yanai et al.
patent: 5566324 (1996-10-01), Kass
patent: 5586294 (1996-12-01), Goodwin et al.
patent: 5586295 (1996-12-01), Tran
patent: 5588128 (1996-12-01), Hicok et al.
patent: 5600817 (1997-02-01), Macon, Jr. et al.
Dahlgren and Stenstrom, "Effectiveness of Hardware-Based Stride and Sequential Prefetching in Shared-Memory Multiprocessors", High Performance Computer Architecture, 1995 Symposium, pp. 68-77 Feb. 1995.
Chen and Baer, "Effective Hardware-Based Data Prefetching for High-Performance Processors", IEEE Transactions on Computers, V. 44, No. 5, pp. 609-623 May 1995.
Chiueh, Tzi-cker, "Sunder: A Programmable Hardware Prefetch Architecture for Numerical Loops", Supercomputing '94, pp. 488-497 1994.
Farkas, Jouppi, and Chow, "How Useful Are Non-blocking Loads, Stream Buffers and Speculative Execution in Multiple Issue Processors", High Performance Computer Architecture, 1995 Symposium, pp. 78-89 Feb. 1995.
Dahlgren et al., "Sequential Hardware Prefetching in Shared-Memory Multiprocess", IEEE Transactions on Parallel and Distributed Systems, vol. 6, No. 7, pp. 733-746. (Note p. 733, Manuscript received Nov. 3, 1993.) Jul. 1995.
Evaluating Stream Buffers as a Secondary Cache Replacement, S. Palacharla and R. Kessler, 1994 IEEE International Symposium on Computer Architecture, 1063-6897/94, pp. 24-33 (1994).
United States Patent Application Serial No. 08/442,740.
International Business Machines Corp.
Kordzik Kelly K.
McBurney Mark E.
Saunders Keith W.
Swann Tod R.
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