Michael John Mayfield

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Cache prefetching of L2 and L3

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate

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Efficient store machine in cache based microprocessor

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate

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Fixed snoop response time for source-clocked multiprocessor...

Electrical computers and digital processing systems: multicomput – Distributed data processing – Client/server
Reexamination Certificate

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Instruction pre-fetching of a cache line within a processor

Electrical computers and digital processing systems: memory – Address formation – Generating prefetch – look-ahead – jump – or predictive address
Patent

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Method and apparatus for livelock prevention in a...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate

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Profile ID: LFUS-PAI-P-64684

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