Computer-aided design and analysis of circuits and semiconductor – Design of semiconductor mask or reticle – Layout generation
Reexamination Certificate
2011-08-16
2011-08-16
Rossoshek, Helen (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Design of semiconductor mask or reticle
Layout generation
C716S051000, C716S052000, C716S053000, C716S054000, C716S056000, C716S110000, C716S111000, C716S112000, C716S136000, C430S005000, C430S030000, C430S394000
Reexamination Certificate
active
08001495
ABSTRACT:
A system and method is provided which predicts problematic areas for lithography in a circuit design, and more specifically, which uses modeling data from a modeling tool to accurately predict problematic lithographic areas. The method includes identifying surface heights of plurality of tiles of a modeled wafer, and mathematically mimicking a lithographic tool to determine best planes of focus for exposure for the plurality of tiles.
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Brunner Timothy A.
Greco Stephen E.
Liegl Bernhard R.
Xiang Hua
International Business Machines - Corporation
MacKinnon Ian D.
Roberts Mlotkowski Safran & Cole P.C.
Rossoshek Helen
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