Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2006-01-12
2010-12-28
Britt, Cynthia (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S744000
Reexamination Certificate
active
07861130
ABSTRACT:
According to an embodiment of the invention, a system for identifying when a running speed of an integrated circuit is within an applied clock speed is provided. A monotonic circuit is configured to receive input data and transmit output data. A completion detection circuit is configured to generate a completion detection signal for the monotonic circuit. A comparator is configured to compare at least the completion detection signal and a clock signal, and configured to emit an error signal if the clock signal arrives before the completion detection signal. A synchronous circuit element is configured to receive at least a portion of the output data and configured to be clock driven by the clock signal. The error signal represents that the clock speed is faster than an operating speed of the monotonic circuit.
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Britt Cynthia
Institute of Computer Science, Foundation for Research and Techn
Steptoe & Johnson LLP
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