System and method of clocking an IP core during a debugging...

Details System and method of clocking an IP core during a debugging... System and method of clocking an IP core during a debugging...

2010-02-04

2011-12-27

Tabone, Jr., John J (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S742000, C714S744000, C714S029000, C714S034000, C714S035000

Reexamination Certificate

active

08086921

ABSTRACT:
According to the invention, an IP core is clocked during a debugging operation by switching from the clock used for testing the device under test to a clock oscillator or any other free-running clock source.

REFERENCES:
patent: 6473727 (2002-10-01), Kirsch et al.
patent: 0 685 793 (1995-12-01), None
patent: 11-259329 (1999-09-01), None
patent: 01/20784 (2001-03-01), None
Gernot Koch et al; Co-Emulation and Debugging of HW/SW-Systems, 1997 IEEE; pp. 120-125.
Sungjoo Yoo et al; Fast Hardware-Software Coverification by Optimistic Execution of Real Processor; 2000 IEEE; pp. 663-668.
ISR off corresponding application PCT/EP02/00503 mailed Feb. 27, 2003.

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