System and method of automated wire and via layout...

Details System and method of automated wire and via layout... System and method of automated wire and via layout...

2007-10-29

2010-06-15

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

07739632

ABSTRACT:
A system and method to optimize a circuit layout, and more particularly, to a system and method of post layout data preparation to optimize a circuit layout and reduce random and systematic wire and via opens and shorts. The method includes stripping existing vias in a design layout and determining design parameters of the design layout including wiring placement and dimensions. The method further includes optimizing via layout by placing vias away from edges of the wiring and adjacent vias. The invention is also directed to a design structure on which a circuit resides.

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