Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1999-08-13
2003-04-22
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C326S038000, C714S719000, C714S724000
Reexamination Certificate
active
06553523
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to verifying the configuration of a programmable logic device, and more particularly to verifying the configuration of a programmable logic device in which the configuration bitstream includes both commands and data.
BACKGROUND OF THE INVENTION
An example programmable logic device (PLD) is the field programmable gate array (FPGA), first introduced by Xilinx, Inc. (Xilinx) in 1985. PLDs such as FPGAs are becoming increasingly popular for use in electronics systems. For example, communications systems employ FPGAs in large measure for their re-programmability. In general, the use of FPGAs continues to grow at a rapid rate because they permit relatively short design cycles, reduce costs through logic consolidation, and offer flexibility in their re-programmability. The capabilities of and specifications for Xilinx FPGAs are set forth in “The Programmable Logic Data Book”, published in 1998 by Xilinx.
Where once a typical FPGA design comprised perhaps 5,000 gates, FPGA designs with 50,000 gates are now common, and FPGAs supporting over 300,000 gates are presently available. New challenges for configuring PLDs and verifying proper configuration have accompanied the growth in programmable logic resources in PLDs.
New systems have been developed to reduce the time required to program large FPGAs. Whereas configuration bitstreams of prior systems generally had a one-to-one correspondence between bits in the bitstream and programmable elements in the FPGA, newer systems use configuration bitstreams that include commands and data. Configuration bitstreams with commands and data generally have fewer bits than prior configuration bitstreams, and therefore reduce programming time by having fewer bits to download to the FPGA. For example, a single command and accompanying data can be used to write the same data to multiple memory cells in the FPGA. Command-based configuration bitstreams are described in detail in U.S. Pat. No. 5,892,961, issued Apr. 6, 1999 and entitled “A Field Programmable Gate Array Having Programmable Instructions in the Configuration Bitstream” as well as in U.S. Pat. No. 6,204,687, filed on Aug. 13, 1999, issued on Mar. 20, 2001, and entitled “Method and Structure for Configuring FPGAS” both references being incorporated by reference herein.
Command-based configuration bitstreams generally reduce the time required to configure an FPGA. However, because the configuration bitstream includes both commands and data, whereas the data read back from the FPGA only includes data (i.e., states of the configuration memory cells, user memory, and storage elements such as flip-flops and latches), a one-to-one comparison of bits of the readback data to bits of the configuration bitstream will not indicate whether the configuration is proper. Therefore, the complications arising from verification of proper configuration of an FPGA via a command-based configuration bitstream may offset the programming advantages.
Additionally, verification of all data may be unnecessary as many values in the non-configuration memory locations change during operation. Thus, having a system and method for distinguishing between data types and specifically verifying the configuration of the configuration memory cells is desirable.
Therefore, a need arises for a system and method to address the above issues.
SUMMARY OF THE INVENTION
The present invention provides a method and system for verifying proper configuration of a programmable logic device (PLD). The present invention is implemented using a host data processing system (the host) coupled to an interface device, which in turn is coupled to the PLD. The host converts the configuration bitstream containing configuration commands and data to a configuration bitmap. The host uses the interface device to download the configuration bitstream to the PLD, thereby configuring the PLD. Once configured, the host commands the interface device to read back data from the PLD. The host creates a readback bitmap from the readback data and the associated commands. The host also generates a mask bitmap that identifies the bits in both the configuration bitmap and the readback bitmap to ignore or mask during the configuration verification process. Note that in accordance with the present application, each location in one bitmap has a corresponding location in the other bitmaps.
To confirm proper configuration, the host determines whether a particular bit is masked by using the mask bitmap. If that bit is not masked, then the host compares the bit in the readback bitmap to the corresponding bit in the configuration bitmap. The host provides an error signal if these bit values are different. The host evaluates the proper configuration of all non-masked bits in the bitmaps. In another embodiment, all bits, including masked bits, are evaluated, thereby eliminating the need for generating a mask bitmap.
REFERENCES:
patent: 5457408 (1995-10-01), Leung
patent: 5752006 (1998-05-01), Baxter
patent: 5892961 (1999-04-01), Trimberger
patent: 6363517 (2002-03-01), Levi et al.
The Programmable Logic Data Book, 1998, published by and available from Xilinx, Inc., 2001 Logic Drive, San Jose, CA 95124.
Allamsetty Chakravarthy K.
Lindholm Jeffrey V.
Chaudry Mujtaba
De'cady Albert
Maunu, Esq. LeRoy D.
Young Edel M.
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