Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output data buffering
Reexamination Certificate
2005-01-04
2005-01-04
Gaffin, Jeffrey (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output data buffering
C710S008000, C710S022000
Reexamination Certificate
active
06839777
ABSTRACT:
A system and method for transferring data over a communications medium using data transfer links. A host computer may couple to a device through a serial bus. A buffer of contiguous virtual memory addresses may correspond to non-contiguous physical addresses, which may be stored in a linked list of transfer nodes, preserving the order of the original virtual buffer elements. Each transfer node specifies a data transfer between the host and device, and may be executed by the device DMA Controller. Each node may contain source and/or destination address information, size of the data to be transferred, and a link to the next node. The transfer nodes may be transferred to the device using a double-buffering scheme wherein the device executes the nodes from one half of the link buffer while the host computer transfers further nodes to be executed to the other half of the link buffer. The buffer halves may be switched back and forth between these two processes until all links are executed. To prevent overruns, safety and message links may be inserted into the transfer link list. The safety link may prevent the DMA channel from executing the next half of the link list until it has been updated by the host. The safety link may then be turned into a connection link. The host may update the used half of the link chain only after it receives a message initiated by the message link that the DMA Channel is done with its half of the linked list.
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Madden David W.
Vrancic Aljosa
Chen Alan S
Gaffin Jeffrey
Hood Jeffrey C.
Meyertons Hood Kivlin Kowert & Goetzel P.C.
National Instruments Corporation
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