System and method for the injection and cancellation of a bias v

Details System and method for the injection and cancellation of a bias v System and method for the injection and cancellation of a bias v

1997-12-22

1999-11-30

Nguyen, Hoa T.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

714721, G01R 3128

Patent

active

059961007

ABSTRACT:
A system and method for injecting and canceling a bias voltage in an attenuated circuit is presented. The attenuated circuit is disposed within a tri-state logic-level measurement apparatus. The bias voltage is provided to ensure that when the measurement apparatus is floating, it floats at the tri-state voltage. In one embodiment, a summing network is connected to an attenuator, a first voltage generator which provides a bias voltage and a second voltage generator which provides a cancellation voltage. In another embodiment, a FET amplifier is provided in place of the summing network.

REFERENCES:
patent: 5179353 (1993-01-01), Miyake
patent: 5383223 (1995-01-01), Inokuchi

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