Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2000-12-29
2003-05-13
Elms, Richard (Department: 2824)
Static information storage and retrieval
Read/write circuit
Testing
C365S230050, C365S233100
Reexamination Certificate
active
06563751
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to sRAMs and, more particularly, to a technique for testing time domain multiplex sRAMs.
BACKGROUND OF THE INVENTION
Time Domain Multiplex (“TDM”) static random access memories (“sRAMs”) have found a wide range of applications in telecommunication application specific integrated circuits (“ASIC”) due to their small area and flexibility.
Time Domain Multiplex sRAM is a new multi-port memory design methodology. In a TDM sRAM, a single set of read/write and address decoding circuitry as well as a single set of word/bit lines are shared among multiple ports in a time slice fashion. Thus, in a single system clock cycle, each port is given a fraction of the cycle time to access the memory through the same read/write circuitry as well as the same address decoder. Compared to a conventional multi-port memory, a TDM sRAM that supports the same number of ports as the conventional one occupies significantly less silicon area. In addition, it draws less peak current. As a result, TDM sRAMs are becoming more and more attractive to telecommunication ASICs, which usually embed a large number of multi-port memories.
The use of TDM sRAMs has helped reduce silicon area of multi-port memories, thus allowing the integration of more functionality into an ASIC. It has also created new challenges for testing. In a single system clock cycle, a TDM sRAM is accessed multiple times through different ports. The fundamental mechanism that supports such multiple accesses in a single clock cycle is an internal clock generator that clocks the core of the TDM sRAM many times faster than the system clock. For a m-port TDM sRAM, the memory core may run m times faster than the circuits that access it. Thus, the memory may run at an internal clock that is m times faster than the system clock. A slow system clock coupled with a fast internal clock creates new challenges for at-speed testing of TDM sRAMs, especially if the test is conducted with built-in self-test (“BIST”) circuitry on boards or in systems.
This slow system clock coupled with fast internal clock makes it difficult to achieve high test quality with conventional BIST techniques, especially for timing related faults. This is because conventional test approaches for TDM sRAM disable the internal clocks and use the system clock to test the memory as if it is a conventional single port memory. The clock generator itself is then tested using scan test vectors.
Since the system clock is usually much slower than the internal clocks, especially when the ASIC is tested on a board or in a system, the conventional test approaches cannot cover timing related defects in the memory. The approach described in U.S. patent application Ser. No. 09/401,976, “At-speed Built-in Self-Testing of Compact SRAM”, herein incorporated by reference, does not provide complete coverage of timing related defects.
In view of the foregoing, it would be desirable to provide a technique for testing TDM sRAMs which overcomes the above-described inadequacies and shortcomings. More particularly, it would be desirable to provide a technique for testing TDM sRAMs in an efficient and cost effective manner.
SUMMARY OF THE INVENTION
According to the present invention, a technique for testing sRAMs is provided. In one embodiment, the technique is realized by a method for testing a static random access memory (“sRAM”). The process includes a technique for testing a static random access memory (“sRAM”) having a plurality of ports is disclosed. In one embodiment, the technique is realized by testing the memory with values through a first port while applying one of a shadow write where a shadow read from a second port and testing the memory through the second port while applying one of the shadow write and the shadow read from the first port. The shadow write may be designed to write specified values into cells of the memory not being tested where the specified values are opposite to values used in testing the memory. The shadow read may be designed to read values from memory that are opposite to the values used in testing the memory, even though the shadow read results are not examined.
In accordance with other aspects of the present invention, the sRAM may be partitioned into two equal portions based on rows and/or columns. Each half of the memory may be tested through each of the ports while a shadow write or shadow read is applied through the other port over the other half of the memory.
In accordance with further aspects of the present invention, a conventional BIST controller may be used to perform the TDM sRAM testing algorithm.
The present invention will now be described in more detail with reference to exemplary embodiments thereof as shown in the appended drawings. While the present invention is described below with reference to preferred embodiments, it should be understood that the present invention is not limited thereto. Those of ordinary skill in the art having access to the teachings herein will recognize additional implementations, modifications, and embodiments, as well as other fields of use, which are within the scope of the present invention as disclosed and claimed herein, and with respect to which the present invention could be of significant utility.
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Nadeau-Dostie, B., SilBurt, A. and Agrawal, V.K., “A Serial Interfacing Technique for External and Built-In Self-Testing of Embedded Memories”, IEEE Design and Test of Computers, vol. 7, No. 2, pp. 54-64, Apr. 1990.
Wu, Y. and Gupta, S., “Built-In Self-Test for Multi-Port RAMs”, Proc. 6thAsian Test Symp., pp. 398-403, Nov. 1997.
van de Goor, A.J., Testing Semiconductor Memories: Theory and Practice, John Wiley & Sons, Ltd., England, 1991.
Elms Richard
Hunton & Williams
Nguyen Hien
Nortel Networks LImited
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