Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2008-04-01
2008-04-01
Lin, Sun James (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
07353472
ABSTRACT:
A system and method for generating test patterns for a pattern sensitive algorithm. The method comprises the steps extracting feature samples from a layout design; grouping feature samples into clusters; selecting at least one area from the layout design that covers a feature sample from each cluster; and saving each pattern layout covered by the at least one area as test patterns.
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DeMaris David L.
Dunham Timothy G.
Leipold William C.
Maynard Daniel N.
Scaman Michael E.
Hoffman Warnick & D'Alessandro LLC
International Business Machines - Corporation
Kotulak Richard M.
Lin Sun James
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