Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2000-01-07
2003-11-18
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S727000
Reexamination Certificate
active
06651198
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates generally to testing of electrical circuits and more particularly to a system and method for testing on-chip modules and the interconnections between on-chip modules in a modularized integrated circuit.
BACKGROUND OF THE INVENTION
Integrated circuits generally consist of several on-chip modules interconnected to form a single integrated circuit. In order to verify the operational integrity of the integrated circuit, the operation of each module must be verified to ensure that the proper output signal is produced for a given input signal. In addition, the interconnections between the modules must be verified to ensure that signals are passed between the modules correctly.
Testing systems, referred to as scan test systems, are designed into the integrated circuit. These test systems allow test signals to be input to each module and the associated output signals can then be verified. In addition, a test signal can be introduced at the origin of an interconnection between two modules and verified at the termination point of the interconnection. The basic component of scan test systems is the scan cell consisting of a multiplexer and a shift register. Each electrical component introduced into the data path of a circuit necessarily causes processing delays within that circuit. Thus, a circuit with two multiplexers on a data path will take longer to process a given input signal than a circuit with only one multiplexer.
Currently, modularized integrated circuit testing is accomplished by a four step process. For purposes of this discussion, Module. A and Module B are interconnected such that the output of Module A is connected to the input of Module B. Standard testing system design inserts two scan cells into the interconnection between two modules. Scan cells can both capture a signal so it can be tested and introduce a test signal to the input of a module so it can be processed. In this example, a first scan cell is attached to the output of Module A, and a second scan cell is attached to the input of Module B. Thus, there is a signal path between the first and second scan cells which connect Module A and Module B. First, a test signal is introduced to the input pins of Module A. The output of Module A is then captured by the first scan cell where it is made available for verification. Second, a test signal is introduced to the second scan cell which is connected to the input of Module B. The second scan cell forwards the test signal to Module B where it is processed, and the output of Module B is then read and verified. Third, the first scan cell, which is connected to the output of Module A, must be verified for a properly functioning signal path. In order to accomplish this, a signal is introduced into the first scan cell and the output of that scan cell is captured and verified. Fourth, the signal path between the first scan cell and the second scan cell must be verified. This is accomplished by introducing a test signal into the first scan cell which is then forwarded to the second scan cell. The test signal is captured by the second scan cell, which is connected to the input of Module B, where it is read and verified. Thus, it takes four steps to verify that Module A, Module B, and the signal path between Module A and Module B operate as intended.
The four-step integrated circuit testing procedure described above is unnecessarily time consuming, and it requires several electrical components. In addition, the necessity of test circuitry built directly into the integrated circuit introduces delays into the normal processing of the integrated circuit. Therefore, the aforementioned integrated circuit testing process is both cumbersome and inefficient.
SUMMARY OF THE INVENTION
From the foregoing, it may be appreciated that a need has arisen for an improved system and method for verifying the operational integrity of the modules within an integrated circuit and the interconnections between those modules. In accordance with the present invention, an improved system and method of testing modules within an integrated circuit and the interconnections between those modules is provided which substantially reduces disadvantages or problems associated with conventional integrated circuit testing procedures.
According to one embodiment of the present invention, there is provided a system for testing the operation of on-chip modules and the interconnections between those on-chip modules that comprises an output scan cell consisting of a multiplexer and a shift register, an input scan cell consisting of a shift register only, and a mode select signal which selects either input signal path testing or output signal path testing. This design allows for complete operational integrity testing in two steps.
REFERENCES:
patent: 3806891 (1974-04-01), Eichelberger et al.
patent: 5260949 (1993-11-01), Hashizume et al.
patent: 5488613 (1996-01-01), Sridhar
patent: 5568492 (1996-10-01), Flint et al.
patent: 5636228 (1997-06-01), Moughanni et al.
patent: 5644261 (1997-07-01), Frisch et al.
patent: 5804960 (1998-09-01), El Ayat et al.
patent: 5911039 (1999-06-01), Hashizume et al.
patent: 6079040 (2000-06-01), Hom et al.
patent: 6191603 (2001-02-01), Muradali et al.
patent: 0 822 497 (1988-02-01), None
“A cost analysis study of deposited-MCM active substrates for testability purposes” Oliver at al1996 IEEE Multi-Chip Module Conference, 1996. MCMC-96, Proceedings., pp.: 80-85Feb. 6-7, 1996.*
“DfT techniques for first-time right MCMs-exemplified by a Pentium MCM system” Wysse et al. 1998 International Conference on Mulitchip Modules and High Density Packaging pp: 190-195, Apr. 15-17, 1998.
Brady W. James
Britt Cynthia
De'cady Albert
Hoel Carlton H.
Telecky , Jr. Frederick J.
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