System and method for testing memory at full bandwidth

Details System and method for testing memory at full bandwidth System and method for testing memory at full bandwidth

2008-01-15

2008-01-15

Lamarre, Guy (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C714S747000, C714S766000

Reexamination Certificate

active

07320096

ABSTRACT:
There is disclosed systems and methods for testing a memory where at least one bit field at certain address locations cannot be directly accessed. In one embodiment, random bits are populated into a data field at one of the certain address locations, and at least some of the random data bits that are copied into non-directly accessible data field. The bits which were copied from the data field are replaced with bits resulting from X/ORing the copied data bits with bits read from the non-directly accessible field, and all the data field bits as the address locations are checked for mismatched data bits.

REFERENCES:
patent: 6223309 (2001-04-01), Dixon et al.
patent: 6408417 (2002-06-01), Moudgal et al.
Affidavit of Richard W. Adkisson, Feb. 17, 2005, 4 pages.

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