Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2001-06-22
2004-03-02
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S726000, C714S729000, C714S733000, C714S737000
Reexamination Certificate
active
06701474
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The field of the present invention relates to electronic design automation and, more particularly, to methods and systems for testing integrated circuits during manufacturing and/or fabrication stages.
2. Background
Circuit chip designers often use electronic design automation (EDA) software tools to assist in the design process, and to allow simulation of a chip design prior to prototyping or production. Chip design using EDA software tools generally involves an iterative process whereby the chip design is gradually perfected. Typically, the chip designer designs a circuit by inputting information at a computer workstation generally having a high quality graphics capability so as to display portions of the circuit design as needed. A top-down design methodology is commonly employed using hardware description languages (HDLs), such as Verilog® or VHDL, for example, by which the designer creates an integrated circuit by hierarchically defining functional components of the circuit, and then decomposing each component into smaller and smaller components.
The various components of an integrated circuit are initially defined by their functional operations and relevant inputs and outputs. From the HDL or other high level description, the actual logic cell implementation is typically determined by logic synthesis, which converts the functional description of the circuit into a specific circuit implementation. The logic cells are then “placed” (i.e., given specific coordinate locations in the circuit layout) and “routed” (i.e., wired or connected together according to the designer's circuit definitions). The placement and routing software routines generally accept as their input a flattened netlist that has been generated by the logic synthesis process. This flattened netlist identifies the specific logic cell instances from a target standard cell library, and describes the specific cell-to-cell connectivity. After this specific cell-to-cell connectivity has been established, the physical design and layout software creates a physical layout file of the integrated circuit, including the physical position of each metal line (i.e., wire) and each via (i.e., metal transition between chip layers).
As a last step before creation of the mask file for delivery to the fabrication facility, the physical verification and layout validation software performs several design rule checks (DRCs) on the layout file. More recently, in order to handle very large and complex designs, a netlist is created for each section or block in the design. The subsequently placed and routed blocks are then hierarchically viewed as “cells” at the next, full design level, and again placed and routed to form the layout of the whole chip. In this hierarchical approach, the DRCs are also performed hierarchically. Further explanation of a particular chip design process is set forth, for example, in U.S. Pat. No. 5,838,583, hereby incorporated by reference as if fully set forth herein.
During fabrication at a semiconductor foundry, integrated circuits are typically manufactured on semiconductor wafers as part of a multi-step process. A single integrated circuit design is generally duplicated numerous times over a single semiconductor wafer, with iterations of the integrated circuit laid out evenly in rows and columns on the semiconductor wafer. Fabrication of a semiconductor wafer containing integrated circuits may involve etching, deposition, diffusion, and cleaning processes, all carried out within specified tolerances.
Typically, some of the integrated circuits on the semiconductor wafer will not be suitable for commercial use due to imperfections in the manufacturing process. The number of integrated circuits on each wafer that will be problematic depends in part on the quality and consistency of the fabrication process. However, despite the often best efforts of semiconductor foundries, there will usually be a number of integrated circuits on each wafer that need to be rejected, even though the design “blueprint” is correct, because during the fabrication process electrical components do not meet the proper tolerances, because electrical connections that should be made are not sufficiently conductive, because electrical paths that should be isolated become too close together or shorted, or because of other imperfections that may occur at any point in the etching, deposition, diffusion or cleaning processes. The endless push to decrease the size of integrated circuits, including the micro-circuitry, wires and components forming a part thereof, merely increases the likelihood that imperfections will occur during the fabrication process requiring rejection of at least some (and sometimes all) of the integrated circuits on a semiconductor wafer.
After the fabrication process, a semiconductor wafer typically goes through a packaging process in which the wafer is diced into dies and then packaged for shipment or integration in electronic devices. The failure to identify problematic integrated circuits before such shipment or integration can be devastating. If an imperfect integrated circuit is not identified before shipping, it may be placed in a product and sold to a consumer or end user, whereupon it will eventually fail during operation. Besides hurting the reputation of the chip designer and semiconductor fabrication facility, such operational failures can also cause major problems to the application of the consumer or end user. Furthermore, the cost of replacing the whole defective product is much greater than removing the defective component from the manufacturing process before it is assembled into the final product.
Consequently, integrated circuits should to be tested to ensure that they will operate properly. Such testing may occur at the point when fabrication of the semiconductor wafer complete and/or after the die has been packaged. A variety of tests have been developed for use during either one of these stages of manufacturing. Most of the tests are administered through a “probe card” connected to an automated machine. The probe card is a test fixture that makes direct contact with the integrated circuit being tested (also known in this context as the “device under test” or “DUT”). In one form, the probe card includes an electrical interface that is compatible with the DUT. The automated machine controlling the probe card generally includes a computer that has various stored test information developed by the design or test engineers specifically for the DUT. The classes of tests carried out may include functional tests, such as diagnostic tests and stress tests, for ensuring that the functionality of the integrated circuit is complete, and structural tests, such as built-in self-tests (BISTs) and scan-based tests, for ensuring that no structural faults exist in the logic of the DUT.
One of the considerations to selecting the type(s) of test to employ for an integrated circuit is the amount of time each test requires. Because integrated circuits are often part of a mass production process, in which tens of thousands or even millions of units may be produced, even relatively short tests can, in the aggregate, result in significant processing delays. Moreover, post-fabrication tests typically require expensive, specialized test equipment, which can run in the tens of thousands or millions of dollars per test machine. Because integrated circuits increasingly include millions or tens of millions of gates, conventional testing techniques are fast becoming either too time-consuming or ineffective at fully testing integrated circuits. For the same reason, the cost of testing is rapidly becoming the most expensive part of manufacturing an integrated circuit.
A drawback with conventional test procedures is that large amounts of data, in the form of test patterns, often need to be transferred between the tester and the internal circuitry of the integrated circuit, via the probe card connected to the integrated circuit. With potentially millions of gates to be te
Cooke Laurence H.
Lennard Christopher K.
Bingham & McCutchen LLP
Cadence Design Systems Inc.
De'cady Albert
Yufa Aleksandr
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