Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2006-10-31
2006-10-31
Kerveros, James C. (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Reexamination Certificate
active
07131046
ABSTRACT:
A system and method that enables testing of circuitry using an externally generated signature. An external tester is arranged external to a device under test (DUT). Such external tester is operable to input test data to the DUT, receive output data from the DUT, and generate a signature for at least a portion of such received output data. The external tester compares the generated signature with an expected signature to determine whether the DUT is functioning as expected. If the generated signature fails to match an expected signature, then error data can be written to an error map log. Preferably, further interaction with the DUT is not required after detecting that a generated signature fails to match an expected signature in order to perform such error evaluation. Thus, error evaluation can be performed concurrently with testing of the DUT. Mask data may be stored in a compressed form, and decompressed and used for masking certain non-deterministic output bits in generating the signature.
REFERENCES:
patent: 4503537 (1985-03-01), McAnney
patent: 4513418 (1985-04-01), Bardell, Jr. et al.
patent: 5051996 (1991-09-01), Bergeson et al.
patent: 5206582 (1993-04-01), Ekstedt et al.
patent: 5313469 (1994-05-01), Adham et al.
patent: 5369648 (1994-11-01), Nelson
patent: 5416783 (1995-05-01), Broseghini et al.
patent: 5583786 (1996-12-01), Needham
patent: 5633877 (1997-05-01), Shephard, III et al.
patent: 5642362 (1997-06-01), Savir
patent: 5668817 (1997-09-01), Adham
patent: 5694401 (1997-12-01), Gibson
patent: 5938784 (1999-08-01), Kim
patent: 5954830 (1999-09-01), Ternullo, Jr.
patent: 5960008 (1999-09-01), Osawa et al.
patent: 5968194 (1999-10-01), Wu et al.
patent: 5978946 (1999-11-01), Needham
patent: 6001662 (1999-12-01), Correale, Jr. et al.
patent: 6158033 (2000-12-01), Wagner et al.
patent: 6199184 (2001-03-01), Sim
patent: 6240537 (2001-05-01), Sim
patent: 6327685 (2001-12-01), Koprowski et al.
patent: 6363506 (2002-03-01), Karri et al.
patent: 6374370 (2002-04-01), Bockhaus et al.
patent: 6393594 (2002-05-01), Anderson et al.
patent: 6442722 (2002-08-01), Nadeau-Dostie et al.
patent: 6452411 (2002-09-01), Miller et al.
patent: 6460152 (2002-10-01), Demidov et al.
patent: 6684358 (2004-01-01), Rajski et al.
patent: 2002/0073374 (2002-06-01), Danialy et al.
Abramovici, Miron et al., “Digital Systems Testing and Testable Design,” IEEE Press, 1990, pp. 432-449.
Bassett, Robert W. et al., “Low-Cost Testing of High-Desnity Logic Components,” IEEE Press, 1990, pp. 15-28.
U.S. Appl. No. 09/802,440, filed Mar. 9, 2001, Khoche et al.
U.S. Appl. No. 10/155,651, filed May 24, 2002, Volkerink et al.
Hilliges Klaus D.
Khoche Ajay
Volkerink Erik H.
Kerveros James C.
Verigy IPco
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