System and method for testing an integrated circuit

Details System and method for testing an integrated circuit System and method for testing an integrated circuit

2007-03-14

2010-06-22

Britt, Cynthia (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S742000

Reexamination Certificate

active

07743295

ABSTRACT:
A system and method for testing an integrated circuit is disclosed. One embodiment includes at least one central processing unit, at least one volatile memory area, and an interface, wherein the volatile memory area is connected to the interface to be written thereto by the interface. The system includes a test device connected with the integrated circuit which is configured to stop the program execution, write data in the volatile memory by using the interface, and start the program execution.

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“Trends in manufacturing test methods and their implications” by Kundu et al. This paper appears in: Test Conference, 2004. Proceedings. ITC 2004. International Publication Date: Oct. 26-28, 2004 on pp. 679-687 ISBN: 0-7803-8580-2 INSPEC Accession No. 8263170.
Motorola Inc.: “Power QUICC—MPC860 User's Manual”, 1998.

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