Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2011-08-02
2011-08-02
Britt, Cynthia (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S720000, C714S735000, C714S742000
Reexamination Certificate
active
07992059
ABSTRACT:
A system and method for replicating a memory block throughout a main memory and modifying real addresses within an address translation buffer to reference the replicated memory blocks during test case set re-executions in order to fully test the main memory is presented. A test case generator generates a test case set (multiple test cases) along with an initial address translation buffer that includes real addresses that reference an initial memory block. A test case executor modifies the real addresses after each test case set re-execution in order for a processor to test each replicated memory block included in the main memory.
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Anvekar Divya Subbarao
Choudhury Shubhodeep Roy
Dusanapudi Manoj
Hatti Sunil Suresh
Kapoor Shakti
Britt Cynthia
International Business Machines - Corporation
McMahon Daniel F
Talpis Matthew B.
VanLeeuwen & VanLeeuwen
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