System and method for synchronizing a selected master...

Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses

Reexamination Certificate

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Reexamination Certificate

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06952789

ABSTRACT:
A mechanism for synchronizing a multiple-circuit system, includes (a) selecting a master circuit from a plurality of circuits, the remaining circuits including at least one slave circuit, (b) receiving, at each of the plurality of circuits, input data and a local clock signal associated with the input data, (d) generating at least one control signal at the master circuit using the local clock signal of the master circuit, (e) outputting the control signal from the master circuit, (f) forwarding the control signal to the slave circuit(s), (g) looping back the control signal to the master circuit, (h) processing the input data at the slave circuit(s) using the forwarded control signal, (i) processing the input data at the master circuit using the looped-back control signal, and (j) outputting the processed data from each of the plurality of circuits.

REFERENCES:
patent: 4310896 (1982-01-01), Cutler et al.
patent: 4509113 (1985-04-01), Heath
patent: 5367697 (1994-11-01), Barlow et al.
patent: 5564114 (1996-10-01), Popat et al.
patent: 6516420 (2003-02-01), Audityan et al.
patent: 58064528 (1983-04-01), None
Software Reset to Second Processor Via Non-Maskable Interrupt, Jul. 1989, IBM Technical Disclosure Bulletin, vol. 32, Issue 2, pp. 86-87.

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