Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses
Reexamination Certificate
2000-02-07
2003-08-05
Lee, Thomas (Department: 2185)
Electrical computers and digital processing systems: support
Synchronization of clock or timing signals, data, or pulses
C707S793000, C709S200000
Reexamination Certificate
active
06604205
ABSTRACT:
TECHNICAL FIELD
The present invention is generally related to the field of computer state control, and, more particularly, is related to a system and method for state synchronization between at least two data handling devices.
BACKGROUND OF THE INVENTION
Technology has become pervasive in nearly all aspects of society. For example, the explosion in digital computing devices has changed the way people live and work. For example, personal computers have become commonplace in homes and in businesses. This computer technology has opened new avenues of communications such as email and other data communications that has provided unprecedented availability to information, for example, on the world wide web (www) of the Internet. In the workplace, for example, computer technology has facilitated telecommuting and other conveniences where employees may work at home and have full access to office computer systems, etc.
With the current mobility of systems, situations arise in which two or more devices are employed to accomplish a particular task(s). For such systems to work in tandem, often information is passed therebetween that is employed to perform the various tasks. This can create a problem in that information may be lost in transit. Consequently, a transmitting device may operate under the assumption that the receiving device has received all transmitted information when is not the case. Thus, the state of the receiving device may not be in a current state for proper operation in light of the current state of the transmitting device.
SUMMARY OF THE INVENTION
In light of the foregoing, a system and method are provided for maintaining state synchronization between a primary device and a secondary device. The method of the present invention comprises the steps of generating a sequence identifier in the primary device, attaching the sequence identifier to a message in the primary device, transmitting the message and the sequence identifier attached thereto to the secondary device, and storing the sequence identifier in the second device. In addition, the present method may optionally include the step of comparing a transmitted sequence identifier from the secondary device with the sequence identifier in the primary device to detect a lost message.
In another embodiment of the present invention, a system is disposed in a primary device for maintaining state synchronization between a primary device and a secondary device. In this regard, the system includes a processor electrically coupled to a local interface and a memory electrically coupled to the local interface. Stored on the memory and executed by the processor is primary sequencing logic. The primary sequencing logic includes logic to generate a sequence identifier, logic to attach the sequence identifier to a message, where the message and the sequence identifier are to be transmitted to the secondary device, and logic to store the sequence identifier for future comparison with sequence identifiers received from the secondary device. Alternatively, the foregoing system may also be implemented in a dedicated logical circuit rather than the processor circuit as described above.
In addition, the present invention provides for a system in a secondary device for maintaining state synchronization between a primary device and a secondary device. In this regard, the system comprises a processor electrically coupled to a local interface and a memory electrically coupled to the local interface. Stored in the memory and executed by the processor is secondary sequencing logic. The secondary sequencing logic includes logic to detect a receipt of a message and a sequence identifier attached thereto from the primary device, logic to store the sequence identifier, and logic to transmit the sequence identifier to the primary device in response to a received state request message from the primary device. Alternatively, the aforementioned system may also be implemented in a dedicated logical circuit rather than the processor circuit as described above.
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Cao Chun
Hewlett-Packard Development Co. L.P.
Lee Thomas
LandOfFree
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