Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1996-02-27
1998-06-09
Gossage, Glenn
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711134, 711147, 39520008, G06F 1314
Patent
active
057651965
ABSTRACT:
In a multiprocessor system having a shared memory, each central processor services copyback requests from other central processors. Each central processor has a writeback buffer along with a plurality of tag buffers and an associated snoop architecture for processing writeback and copyback commands. Each central processor includes a cache subsystem having a system interface, a main cache and an associated tag array. The system interface has an address controller and data controller, each having separate input and output queues for interfacing between the central processor and system control and data buses. The address controller includes a set of duplicate tags that mirror the tags associated with the main cache, and an auxiliary tag input buffer and auxiliary tag output buffer. The address controller has for each line in the output queue an associated pointer that indicates the location in the data controller where data is stored that is associated with output queued commands. In operation, the address controller processes inbound multiple copyback requests without requiring the central processor to access data from its associated main cache. The address controller utilizes the output queues in the address and data controller as well as the auxiliary tag buffers to store copyback data and tag information.
REFERENCES:
patent: 5530933 (1996-06-01), Frink et al.
patent: 5581729 (1996-12-01), Nishtala et al.
patent: 5644753 (1997-07-01), Ebrahim et al.
Broniarczyk David J.
Liencres Bjorn O.
Singhal Ashok
Gossage Glenn
Sun Microsystems Inc.
Williams Gary S.
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