System and method for sequential testing of high speed...

Details System and method for sequential testing of high speed... System and method for sequential testing of high speed...

2007-03-13

2007-03-13

Ton, David (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Transmission facility testing

C714S716000, C714S733000

Reexamination Certificate

active

10118751

ABSTRACT:
A testing circuit for testing a series of at least three alternating transmitter and receiver links. The testing circuit including a built-in-self-test (BIST.) macro for generating test data and transmitting the test data to a first link of the series of transmitter and receiver links, and for receiving processed test data from a last link of the series of transmitter receiver links; and at least one test transmission line for transmitting test data received by a link of the series of transmitter and receiver links to a next link of the series of transmitter and receiver links, wherein the at least one test transmission line connects the at least three transmitter and receiver links. A method for testing a series of links having at least three alternating transmitter and receiver links of a plurality of transmitter and receiver links in a SerDes core including generating at least one test data signal; transmitting the at least one test data signal sequentially through the transmitter and receiver links of the series of links; receiving the at least one test data signal from a last link of the series of transmitter and receiver links; and checking the at least one test data signal received.

REFERENCES:
patent: 5787114 (1998-07-01), Ramamurthy et al.
patent: 5956370 (1999-09-01), Ducaroir et al.
patent: 6542096 (2003-04-01), Chan et al.
patent: 6581063 (2003-06-01), Kirkman
patent: 6661786 (2003-12-01), Abbiate et al.
patent: 6701476 (2004-03-01), Pouya et al.

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