Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
Reexamination Certificate
1999-04-29
2001-10-30
Nguyen, Than (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Shared memory area
C711S147000, C711S148000, C711S149000, C711S150000, C711S151000, C711S153000, C711S163000, C711S164000
Reexamination Certificate
active
06311255
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to computer systems with shared memory, and more particularly to computer systems requiring security, reliability, recoverability and data integrity for two or more bus adapters utilizing a common physical memory.
BACKGROUND OF THE INVENTION
Typical server systems need to be connected to a variety of adapters to provide connectivity and high speed access to data. One prevalent means of doing so is through a local bus, such as the PCI bus (Peripheral Component Interconnect). The PCI bus supports multiple adapters on a single bus, and provides high data transfer capabilities. Example adapters could provide network connectivity or high speed access to data. One adapter might provide Fibre Channel connectivity another might provide (IBM) ESCON connectivity. These connections might provide connectivity to DASD storage, network switches or other devices known in the art. The Local Bus (such as PCI in this example) connection of these Adapters permits flexibility in configuring a system since a variety of adapter functions can be chosen that best fit the system requirement. These adapters are normally plugable modules or cards but some could be “hard wired” into the system or could be cable connected as is known in the art.
Consider a configuration where multiple adapters providing network connectivity or high speed access to data (storage attachments like Fiber Channel, ESCON and so on) are connected to a processor, with its local memory, through the PCI bus. These PCI-based adapters could be off-the-shelf firmware created by vendors for the mass market or these could be custom built for the firmware configuration at hand. Typical server systems need to be connected to a variety of adapters to provide connectivity and high speed access to data. One prevalent means of doing so is through a local bus, such as the PCI (Peripheral Component Interconnect) bus. The PCI bus supports multiple adapters on a single bus, and provides high data transfer capabilities.
Although PCI based components are designed to conform to a standard, there are numerous occasions when the incompatibilities between the different components in the system, or bugs in the code, can cause the PCI bus to hang. When this happens, data transfers across the bus come to a halt, since the bus is now inaccessible to all agents. Moreover, the only reliable way of resuming operation is to assert a PCI RST# (reset) signal, which also has the undesirable effect of resetting all the trapped error information in the PCI agents. Thus, there is little information to aid in debug efforts, and little reliability can be achieved due to the lack of proper recovery from such a situation.
Typically, the processor program (software) partitions the memory map of the PCI system and allocates memory to each unit or adapter on the bus. Thus, the local data store or (LDS) of the processor complex could have different regions. One region is a user area which is accessible to all units. A second region is for exclusive use of a first unit. The memory map might include any combination of these regions. One important exclusive-use area in this LDS would be memory reserved for the exclusive use of the processor complex unit. This would be the area where the processor stores code to execute, possibly including code used to recover from an error condition.
There is a need to protect certain areas of memory so that only adapters/units on the bus that have been defined to have access authorization to the protected area are able to write to those areas. Without this, an errant adapter (through a micro code or hardware failure) could trash key areas of memory and corrupt it and thus exposing the system to unpredictable results. For example, an errant LAN adapter on the bus could overwrite certain recovery routines in the area of memory where the processor complex has stored such routines. Subsequent recovery action in the system would fail and produce unexpected results.
As explained in the example above and in some other instances the configuration of a PCI address map contains regions of memory deemed protected whose access is restricted to the processor alone. An errant access to this protected region of memory, either due to a hardware or code problem, results in an aborted access on the PCI bus, which manifests itself either as a PCI Target Abort or a PCI Master Abort. There are several other scenarios which cause a similar response on the PCI bus, thus making it difficult to tell one scenario from the other. Fault isolation under such conditions becomes extremely difficult, time consuming and costly and may influence customer satisfaction. This problem becomes even more serious when used with over the shelf components, be it PCI or any other bus. The main reason is that many off-the-shelf type hardware that is often used by most manufacturers does not afford the flexibility to isolate errors with any appreciative granularity. This results in generic error or FRU calls, including replacing of complete I/O subsystems, since detailed information about the error is not available. Therefore, a new system is needed that can isolate errors and provide memory protection. The new system needs to eliminate or substantially reduce debug time by pinpointing the kind of error, as well as making FRU calls easier to handle by pinpointing the source of the error.
The present application is being filed on the same day as related U.S. application Ser. No. 09/301,948 titled “Method and Apparatus for Bus Hang Detection and Identification of Errant Agent for Fail Safe Access to Trapped Error Information.”
SUMMARY OF THE INVENTION
It is an object of the present invention to allow areas of local memory on a local bus to be protected for the exclusive use of individual agents on the bus.
It is another object of the present invention to check for illegal access to protected memory by adapters on a local bus.
It is also another object of the present invention to terminate illegal accesses to protected memory by adapters not authorized to use the memory segment being targeted by the errant access.
It is still another object of the present invention to store status information resulting from an illegal access to identify the errant agent on the bus.
It is yet another object of this invention to provide fail-safe access to the processor to this status information, so that appropriate action can be taken, including, but not limited to, a FRU (Field Replacement Unit) call, which would identify errant hardware to the operator for remedial action.
It is also another object of this invention to uniquely identify the adapter that is associated with a memory access by use of the bus arbitration protocol.
A method and apparatus for selectively restricting access to a shared memory is presented in a computer network system having at least one bus capable of attaching a plurality of units to a shared memory. A first adapter unit is attached to the bus initiating a first address on the bus to access the shared memory and the adapter unit establishes control over the bus. An ID circuit is also provided that is in processing communication with the adapter and the bus for associating an adapter address to a unit id, where the circuit id is capable of detecting when a first ID belongs to the first adapter that has been given control of said bus. A memory control unit is attached to the bus for utilizing the first address for accessing said shared memory. An address checker circuit is in processing communication with the bus and is provided. The checker circuit is capable of associating a second address with a second adapter ID. An error generator is also provided for comparing values of the first address and first adapter ID to the second adapter ID and address to one another which will generate an error indicator when the values agree.
REFERENCES:
patent: 5388254 (1995-02-01), Betz et al.
patent: 5428766 (1995-06-01), Seaman
patent: 5475858 (1995-12-01), Gupta et al.
patent: 5499346 (1996-03-01), Amini et al.
patent: 5513319 (1
Gonzalez Floyd A.
International Business Machines - Corporation
Neff Lily
Nguyen Than
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