Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Reexamination Certificate
1998-04-23
2001-12-11
Gossage, Glenn (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
C711S005000, C710S061000, C710S035000, C713S400000, C713S501000, C365S233100
Reexamination Certificate
active
06330650
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a controller provided on a circuit board along with memory modules so as to control the memory modules, each memory module comprising a source synchronous DRAM which, like a synchronous DRAM, outputs a strobe signal in synchronism with read data and transfers the read data. More particularly, the present invention relates to a data receiver incorporated in the controller and capable of performing high-speed, reliable synchronous data transfer with reference to the memory module.
In general, a semiconductor memory is used as a DIMM (Dual Inline Memory Module) when it is incorporated in a personal computer, etc. Eight or sixteen memory chips are provided on the board of the DIMM, and data or signals are input or output by way of connector pins printed on both sides of the board. A memory board employed in a personal computer or the like has four sockets and a controller, and four DIMMs can be provided on the memory board.
FIG. 1
is a conceptual illustration of a memory board on which a controller
151
and four DIMMs (DIMM
1
to DIMM
4
) are provided. In order to control the memory chips of the DIMMs in synchronism with one another, four clocks CLK are sent from the controller
151
to the four DIMMs in parallel. From the DIMMs, 64-bit parallel data are simultaneously transferred by way of a common data bus.
What becomes a problem with this type of memory board is the timing at which the controller fetches data supplied from each DIMM. Since the distance between the controller and one DIMM differs from that between the controller and another DIMM, the flight time (the time needed for a signal to propagate from one point to another, one point corresponds to the controller, and the second point corresponds to a DIMM) of clock signals and data inevitably differs, depending upon the DIMMs. In other words, the data fetch timing has to be controlled by detecting which DIMM is accessed by the controller.
In order to solve the problems described above, 4-bit strobe signals QS are output in parallel from the DIMMs and supplied to the controller. In the example shown in
FIG. 1
, the transfer lines through which data DQ and strobe signals QS are sent are under the same load condition, and a 1-bit strobe signal QS is used for each 16-bit data DQ. The controller monitors the strobe signals QS so as to fetch data in synchronism with the receipt of the strobe signals QS.
FIG. 2
shows how clock signal CLK, data, and strobe signal QS are related to one another when the data transfer is executed according to a so-called DDR (Double Date Rate) system, i.e., a system in which 2-bit data are output in response to the rise of clock signal CLK. In
FIG. 2
, the data transfer from DIMM
1
and DIMM
4
is also shown, so as to indicate how the signal transmission times are different for the DIMMs. Although DIMM
1
and DIMM
2
do not simultaneously output data in practice, they are depicted as doing so, so as to indicate the time relationships between them.
When a clock CLK is supplied from the controller to each DIMM, the time needed for the clock CLK to reach DIMM
4
is longer than the times needed for the same clock CLK to reach the other DIMMs. Although the memories of the DIMMs output data in synchronism with the clock CLK, the output timings are naturally different. In addition, since the data output from the DIMMs require different lengths of time to reach the controller, the difference between the timings at which the controller receives data inevitably increases. This being so, the controller cannot receive data in synchronism with the clocks CLK; it fetches data, with the strobe signal QS used as a trigger signal. The data window based on which data is fetched in synchronism with the strobe signal QS is restricted due to a so-called skew, i.e., the difference between the timings of data and strobe signals. In
FIG. 2
, the time indicated by the oblique lines corresponds to the data window. In order to reliably fetch data within a very restricted time range even in a case where the data is supplied to the controller in an asynchronous manner, the data receiver incorporated in the controller to receive data DQ has to be specially designed.
BRIEF SUMMARY OF THE INVENTION
The present invention has been conceived in consideration of the above problems, and an object of the invention is to provide a data receiver and a memory system that enable accurate control of the data fetch timing even if data are transferred from the memory module to the controller without reference to the system clocks due to irregular flight times.
A data receiver according to the present invention comprises a first receiver and a second receiver. The first receiver receives a plurality of strobe signals, which are supplied thereto along with data, in synchronism with a plurality of first clocks, and generates actuation signals to be supplied to the second receiver. The second receiver receives data, which are supplied thereto along with the plurality of strobe signals, in synchronism with a plurality of second clocks, which have predetermined phase differences with respect to the respective first clocks. Based on this control, the data can be fetched in a reliable manner even if the data and strobe signals are supplied to the data receiver at timings that are made irregular due to various factors.
The present invention provides a data receiver adapted for use in a system wherein data transfer is performed based on data and strobe signals which are supplied to the system simultaneously with the data. The data receiver is made up of: a plurality of first receivers, driven at predetermined time intervals, for receiving the strobe signals; and at least one second receiver, driven based on outputs from the first receivers, for receiving and transferring the data.
The present invention also provides a data receiver adapted for use in a system wherein data transfer is performed based on data and strobe signals which are supplied to the system simultaneously with the data and represent time positions of the data. The data receiver is made up of: a multiphase clock generator for generating a plurality of clocks which have predetermined phase differences and are the same in period; a first receiver which includes units corresponding in number to the multiphase clocks generated by the multiphase clock generator, the units receive the strobe signals in response to the multiphase clocks, maintain states of the received strobe signals for a predetermined length of time, and then output the states of the strobe signals; a second receiver which receives an actuating signal and transfer states of the received data; and a circuit which generates the actuating signal to be supplied to the second receiver, on the basis of an output from the first receiver.
The present invention further provides a data receiver adapted for use in a system wherein data transfer is performed based on data and strobe signals which are supplied to the system simultaneously with the data and represent time positions of the data. The data receiver is made up of: a multiphase clock generator for generating a plurality of clocks which have predetermined phase differences and are the same in period; a first receiver which includes units corresponding in number to the multiphase clocks generated by the multiphase clock generator, the units receive the strobe signals in response to the multiphase clocks, maintain states of the received strobe signals for a predetermined length of time, and then output the states of the strobe signals; a second receiver which includes units corresponding in number to the multiphase clocks generated by the multiphase clock generator, responds to unit actuating signals at respective ones of the units, receives data in response to the multiphase clocks, and transfers the received data; a circuit which generates the unit actuating signals to be supplied to the second receiver on the basis of an output from the first receiver.
The present invention further provides a data receiver ad
Kuyama Hitoshi
Toda Haruki
Banner & Witcoff , Ltd.
Gossage Glenn
Kabushiki Kaisha Toshiba
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