System and method for scalable clock gearing mechanism

Details System and method for scalable clock gearing mechanism System and method for scalable clock gearing mechanism

2007-07-24

2007-07-24

Perveen, Rehana (Department: 2116)

Electrical computers and digital processing systems: support

Synchronization of clock or timing signals, data, or pulses

C713S500000, C713S503000

Reexamination Certificate

active

10748836

ABSTRACT:
In some embodiments, a system and method for making a scalable clock gearing mechanism may allow multiple devices operating on different clock speeds to communicate. In an embodiment, a mechanism may be used to input data clocked on a first clock frequency and output the data on a second clock frequency. The mechanism may temporarily store the data until the next clock cycle of the second clock. Further, the mechanism may make use of multiple inputs or outputs to input or output multiple data units during a single clock cycle to keep the delay between the arrival and departure of the data small.

REFERENCES:
patent: 5905766 (1999-05-01), Nguyen
patent: 5909563 (1999-06-01), Jacobs
patent: 6128749 (2000-10-01), McDonnell et al.
patent: 6765932 (2004-07-01), Santahuhta
patent: 2004/0193936 (2004-09-01), Kelly

Affiliated with

Also associated with

Rating

System and method for scalable clock gearing mechanism does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with System and method for scalable clock gearing mechanism, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System and method for scalable clock gearing mechanism will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3723286