Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses
Reexamination Certificate
2000-06-30
2004-02-17
Lee, Thomas (Department: 2185)
Electrical computers and digital processing systems: support
Synchronization of clock or timing signals, data, or pulses
C713S401000, C713S500000, C713S501000, C713S502000, C713S503000, C327S309000, C327S321000, C327S322000
Reexamination Certificate
active
06694444
ABSTRACT:
BACKGROUND
1. Field of the Invention
This invention relates to semiconductor devices. In particular, the invention relates to buffer circuits.
2. Description of Related Art
Signal integrity is a key issue for front side bus input/output (I/O) buffer design. As processor clock rates become higher and higher, semiconductor process is faster and faster causing many signal integrity problems. In a system where a processor receives signal on the bus, the signal may be subject to high overshoot and ringback. For example, a processor operating at a supply voltage Vcc of 1.5V may experience a signal overshoot of 2.1V and a ringback up to 0.95V. Such a high signal overshoot may lead to gradual oxide degradation impacting silicon life time.n A large ringback may create a push-out in the signal flight time.
Existing techniques to solve ringbacks and overshoots at the receiver have a number of drawbacks. One approach is to use self-timed circuits to generate an appropriate clamping pulse. Another approach is to use separate receiver and driver clamping circuits. These approaches require considerable amount of silicon area. In addition, these approaches may not work with signals running at high clock rates.
Therefore, there is a need to have an efficient technique that can reduce signal overshoot and ringback.
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IBM TDB, vol. 24, issue 4, p. #2199-2200, Title:“Dynamic Differential Sense Amplifier Register”Dtd. Sep. 1, 1981.
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Lee Thomas
Patel Nitin C.
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